xa3s1400a-4ftg256q Xilinx Corp., xa3s1400a-4ftg256q Datasheet - Page 53

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xa3s1400a-4ftg256q

Manufacturer Part Number
xa3s1400a-4ftg256q
Description
Xa Spartan-3a Automotive Fpga Family Data Sheet
Manufacturer
Xilinx Corp.
Datasheet
Table 54: Configuration Timing Requirements for Attached Parallel NOR Flash
DS681 (v1.1) February 3, 2009
Product Specification
Notes:
1.
2.
3.
T
(t
T
(t
T
(t
T
(t
ACC
CE
ELQV
OE
GLQV
AVQV
BYTE
FLQV,
Symbol
These requirements are for successful FPGA configuration in BPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
Subtract additional printed circuit board routing delay as required by the application.
The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s PUDC_B pin is High or Low.
)
)
)
t
FHQV
)
R
Parallel NOR Flash PROM chip-select time
Parallel NOR Flash PROM output-enable time
Parallel NOR Flash PROM read access time
For x8/x16 PROMs only: BYTE# to output valid time
Description
www.xilinx.com
(3)
T
ACC
50%T
T
CCLKn min
T
T
BYTE
CE
OE
Requirement
(
T
T
T
INITADDR
INITADDR
INITADDR
)
T
CCO
T
DCC
PCB
Units
ns
ns
ns
ns
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