xc5210 Xilinx Corp., xc5210 Datasheet - Page 24

• Manufacturer Part Number: xc5210
• Description: Logic Cell Array Family , Inc
• Manufacturer: Xilinx Corp.

XC5200 Logic Cell Array Family
Table 6.
Table 7.
Data Type
Fill Byte
Preamble
Length Counter
Fill Byte
Start Byte
Data Frame *
Cyclic Redundancy Check or
Constant Field Check
Fill Nibble
Extend Write Cycle
Postamble
Fill Bytes (30)
Legend:
Bits per Frame = (34 x number of Rows) + 28 for the
top + 28 for the bottom + 4 splitter bits + 8 start bits + 8
error check bits + 4 fill bits + 4 extended write bits
Number of Frames = (12 x number of Columns) + 7 for
the left edge + 8 for the right edge + 1 splitter bit
Program Data = (Bits per Frame x Number of Frames)
+ 48 header bits + 8 postamble bits + 280 fill bits
PROM Size = Program Data
XC5202
XC5204
XC5206
XC5210
XC5215
Device
(unshaded)
(light)
(dark)
Unified XC5200 Bitstream Format
Internal Configuration Data Structure
VersaBlock
10 x 12
14 x 14
18 x 18
22 x 22
Array
8 x 8
Only once per bitstream
Once per data frame
Once per device
106,320
165,520
237,776
PROM
42,448
70,736
(bits)
Size
Value
11111111
11110010
COUNT(23:0)
11111111
11111110
DATA(N-1:0)
CRC(3:0) or
0110
1111
FFFFFF
11111110
FFFF…FF
Serial Prom
XC17128
XC17256
XC17256
Needed
XC1765
XC1728
Xilinx
20
Figure 17. Start-up Sequence
(*only when PROGRAM = High)
SAMPLE PRELOAD
SAMPLE/PRELOAD*
SAMPLE/PRELOAD
Boundary Scan
CONFIGURE*
Instructions
CONFIGURE
Available:
EXTEST*
BYPASS
BYPASS
READBACK
BYPASS
EXTEST
USER 1
USER 2
Goes Active after
Master CCLK
50 to 250 s
If Boundary Scan
is Selected
F
One Time-Out Pulse
Completely Clear
Data to DOUT
Count Equals
Configuration
Configuration
Configuration
Operational
Mode Lines
Data Frame
Sequence
Yes
Load One
Yes
Yes
Yes
Generate
No
Start-Up
Memory
High? if
Sample
memory
of 4 ms
Config-
Length
Master
Frame
uration
CCLK
Count
Error
Pass
V CC
INIT
Full
3V
Yes
No
No
No
No
~1.3 s per Frame
Pull INIT Low
and Stop
PROGRAM
= Low
Preliminary
Yes
X6037