xc5210 Xilinx Corp., xc5210 Datasheet - Page 33

• Manufacturer Part Number: xc5210
• Description: Logic Cell Array Family , Inc
• Manufacturer: Xilinx Corp.

IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from
benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating
conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the
XACT timing calculator and used in the simulator.
Description
Input
Propagation Delays from CMOS or TTL Levels
Output
Propagation Delays to CMOS or TTL Levels
Note:
Pad to I (no delay)
Pad to I (with delay)
Output (O) to Pad (fast)
Output (O) to Pad (slew-limited)
3-state to Pad active (fast)
3-state to Pad active (slew-limited)
Internal GTS to Pad active (fast)
Internal GTS to Pad active (slew-limited)
1.
2.
Timing is measured at pin threshold, with 50-pF external capacitance loads. Slew-limited output rise/fall times are
approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce,
see pages 8-8 through 8-10 of the 1994 Xilinx Programmable Logic Data Book.
Unused and unbonded IOBs are configured by default as inputs with internal pull-up resistors.
29
Speed Grade
Symbol
T
T
T
T
T
T
T
T
PI
PID
OPF
OPS
TSONF
TSONS
GTSF
GTSS
Max
(ns)
17.7
22.3
11.1
11.6
-6
5.4
4.6
9.4
6.9
Max
(ns)
10.2
10.4
15.9
19.7
-5
4.9
4.5
8.3
6.6
Max
(ns)
-4
R