xc6vcx75t Xilinx Corp., xc6vcx75t Datasheet - Page 42

no-image

xc6vcx75t

Manufacturer Part Number
xc6vcx75t
Description
Virtex-6 Cxt Family Data Sheet
Manufacturer
Xilinx Corp.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC6VCX75T
Manufacturer:
XILINX
0
Part Number:
xc6vcx75t-1FF484C
Manufacturer:
XILINX
Quantity:
624
Part Number:
xc6vcx75t-1FF484C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
xc6vcx75t-1FF484C
Manufacturer:
XILINX
0
Part Number:
xc6vcx75t-1FF484I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
xc6vcx75t-1FF784C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
xc6vcx75t-1FFG484C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
xc6vcx75t-1FFG784C
Manufacturer:
XILINX
Quantity:
13
Part Number:
xc6vcx75t-1FFG784I
Manufacturer:
XilinxInc
Quantity:
3 000
Configuration Switching Characteristics
Table 52: Configuration Switching Characteristics
DS153 (v1.4) July 28, 2010
Advance Product Specification
Power-up Timing Characteristics
T
T
T
T
Master/Slave Serial Mode Programming Switching
T
T
T
F
F
F
SelectMAP Mode Programming Switching
T
T
T
T
T
T
F
F
F
Boundary-Scan Port Timing Specifications
T
T
F
F
F
PL
POR
ICCK
PROGRAM
DCCK
DSCCK
CCO
MCCK
MCCKTOL
MSCCK
SMDCCK
SMCSCCK
SMCCKW
SMCKCSO
SMCO
SMCKBY
SMCCK
RBCCK
MCCKTOL
TAPTCK
TCKTDO
TCK
TCKB_MIN
TCKB
(1)
(1)
/T
/T
/T
CCKD
/T
/T
SCCKD
/T
TCKTAP
SMCCKD
SMWCCK
SMCCKCS
Symbol
Program Latency
Power-on-Reset
CCLK (output) delay
Program Pulse Width
DIN Setup/Hold, slave mode
DIN Setup/Hold, master mode
DOUT at 2.5V
DOUT at 1.8V
Maximum Frequency, master mode with respect to
nominal CCLK
Frequency Tolerance, master mode with respect to
nominal CCLK
Slave mode external CCLK
SelectMAP Data Setup/Hold
CS_B Setup/Hold
RDWR_B Setup/Hold
CSO_B clock to out
(330 Ω pull-up resistor required)
CCLK to DATA out in readback at 2.5V
CCLK to DATA out in readback at 1.8V
CCLK to BUSY out in readback at 2.5V
CCLK to BUSY out in readback at 1.8V
Maximum Frequency with respect to nominal CCLK
Maximum Readback Frequency with respect to nominal
CCLK
Frequency Tolerance with respect to nominal CCLK
TMS and TDI Setup time before TCK/ Hold time after
TCK
TCK falling edge to TDO output valid at 2.5V
TCK falling edge to TDO output valid at 1.8V
Maximum configuration TCK clock frequency
Minimum boundary-scan TCK clock frequency when
using IEEE Std 1149.6 (AC-JTAG). Minimum operating
temperature for IEEE Std 1149.6 is 0°C.
Maximum boundary-scan TCK clock frequency
(1)
www.xilinx.com
Description
Virtex-6 CXT Family Data Sheet
4.0/0.0
4.0/0.0
4.0/0.0
4.0/0.0
9.0/0.0
3.0/2.0
15/55
400
250
100
100
100
100
Speed Grade
55
55
66
15
66
-2
3
6
6
7
8
8
6
6
6
6
4.0/0.0
4.0/0.0
4.0/0.0
4.0/0.0
9.0/0.0
3.0/2.0
15/55
400
250
100
100
100
100
55
55
66
15
66
-1
3
6
6
7
8
8
6
6
6
6
ms, Min/Max
MHz, Max
MHz, Max
MHz, Max
MHz, Max
MHz, Max
MHz, Min
ms, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
MHz
%
%
42

Related parts for xc6vcx75t