xc6vcx75t Xilinx Corp., xc6vcx75t Datasheet - Page 46

• Manufacturer Part Number: xc6vcx75t
• Description: Virtex-6 Cxt Family Data Sheet
• Manufacturer: Xilinx Corp.

MMCM Switching Characteristics
Table 57: MMCM Specification
DS153 (v1.4) July 28, 2010
Advance Product Specification
Notes:
1.
2.
3.
4.
5.
6.
F
F
F
F
F
F
F
F
F
T
T
T
T
F
F
T
RST
F
F
T
T
T
T
T
T
INMAX
INMIN
INJITTER
INDUTY
MIN_PSCLK
MAX_PSCLK
VCOMIN
VCOMAX
BANDWIDTH
STATPHAOFFSET
OUTJITTER
OUTDUTY
LOCKMAX
OUTMAX
OUTMIN
EXTFDVAR
PFDMAX
PFDMIN
FBDELAY
MMCMDCK_PSEN
MMCMCKD_PSEN
MMCMDCK_PSINCDEC
MMCMCKD_PSINCDEC
MMCMCKO_PSDONE
The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
The static offset is measured between any MMCM outputs with identical phase.
Values for this parameter are available in the Architecture Wizard.
Includes global clock buffer.
Calculated as F
When CASCADE4_OUT = TRUE, F
MINPULSE
Symbol
/
VCO
/
/128 assuming output duty cycle is 50%.
Maximum Input Clock Frequency
Minimum Input Clock Frequency
Maximum Input Clock Period Jitter
Allowable Input Duty Cycle: 19—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum Dynamic Phase Shift Clock Frequency
Maximum Dynamic Phase Shift Clock Frequency
Minimum MMCM VCO Frequency
Maximum MMCM VCO Frequency
Low MMCM Bandwidth at Typical
High MMCM Bandwidth at Typical
Static Phase Offset of the MMCM Outputs
MMCM Output Jitter
MMCM Output Clock Duty Cycle Precision
MMCM Maximum Lock Time
MMCM Maximum Output Frequency
MMCM Minimum Output Frequency
External Clock Feedback Variation
Minimum Reset Pulse Width
Maximum Frequency at the Phase Frequency Detector
with Bandwidth Set to High or Optimized
Maximum Frequency at the Phase Frequency Detector
with Bandwidth Set to Low
Minimum Frequency at the Phase Frequency Detector
Maximum Delay in the Feedback Path
Setup and Hold of Phase Shift Enable
Setup and Hold of Phase Shift Increment/Decrement
Phase Shift Clock-to-Out of PSDONE
OUTMIN
is 0.036 MHz.
(3)
Description
www.xilinx.com
(1)
(1)
(5)(6)
(2)
(4)
< 20% of clock input period or 1 ns
< 20% of clock input period or 1 ns
3 ns Max or one CLKIN cycle
1.04/0.00
1.04/0.00
10.00
1200
0.01
1.00
4.00
0.12
0.20
4.69
0.38
700
450
600
100
700
450
300
1.5
10
-2
Speed Grade
Virtex-6 CXT Family Data Sheet
25/75
30/70
35/65
40/60
45/55
Max
Max
Note 1
1.04/0.00
1.04/0.00
10.00
1200
0.01
1.00
4.00
0.12
0.20
4.69
0.38
700
450
600
100
700
450
300
1.5
10
-1
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
µs
ns
ns
ns
ns
ns
ns
%
%
%
%
%
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