ksz8021rnli Micrel Semiconductor, ksz8021rnli Datasheet - Page 11

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ksz8021rnli

Manufacturer Part Number
ksz8021rnli
Description
10base-t/100base-tx Phy With Rmii Support
Manufacturer
Micrel Semiconductor
Datasheet
Micrel, Inc.
Strapping Options – KSZ8021RNL / KSZ8031RNL
Note:
1.
August 2010
Pin Number
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
The PHYAD[1:0] strap-in pin is latched at the de-assertion of reset. In some systems, the RMII MAC receive input pin may drive high/low during
power-up or reset, and consequently cause the PHYAD[1:0] strap-in pin, a shared pin with the RMII CRS_DV signal, to be latched to the
unintended high/low states. In this case, an external pull-up (4.7K) or pull-down (1.0K) should be added on the PHYAD[1:0] strap-in pin to ensure
the intended value is strapped-in correctly.
15
23
ANEN_SPEED
PHYAD[1:0]
Pin Name
Type
Ipd/O
Ipu/O
(1)
Pin Function
The PHY Address is latched at the de-assertion of reset and is configurable to either
one of the following two values:
PHY Address bits [4:2] are set to ‘000’ by default.
Auto-Negotiation Enable and SPEED mode
At the de-assertion of reset, this pin value is latched into register 0h bit [12] for Auto-
negotiation enable/disable, register 0h bit [13] for the Speed select, and register 4h
(Auto-Negotiation Advertisement) for the Speed capability support.
Pull-up = PHY Address is set to 00011b (0x3h)
Pull-down (default) = PHY Address is set to 00000b (0x0h)
Pull-up (default) = Enable Auto-Negotiation and set 100Mbps Speed
Pull-down = Disable Auto-Negotiation and set 10Mbps Speed
11
KSZ8021RNL / KSZ8031RNL
M9999-082710-1.0

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