ksz8021rnli Micrel Semiconductor, ksz8021rnli Datasheet - Page 15

• Manufacturer Part Number: ksz8021rnli
• Description: 10base-t/100base-tx Phy With Rmii Support
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
RMII Data Interface
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides
a common interface between physical layer and MAC layer devices, and has the following key characteristics:
RMII Signal Definition
The following table describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0], and
RXER.
For RMII – 25MHz Clock Mode, the KSZ8021/31RNL generates and outputs the 50MHz RMII REF_CLK to the MAC at
REF_CLK (Pin 16).
For RMII – 50MHz Clock Mode, the KSZ8021/31RNL takes in the 50MHz RMII REF_CLK from the MAC or system board
at XI (Pin 8) and has the REF_CLK (pin 16) left as a no connect.
Transmit Enable (TXEN)
TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first
dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII, and is negated
prior to the first REF_CLK following the final dibit of a frame.
TXEN transitions synchronously with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TXEN is asserted, TXD[1:0] are accepted for
transmission by the PHY.
TXD[1:0] is ”00” to indicate idle when TXEN is de-asserted. Values other than “00” on TXD[1:0] while TXEN is de-asserted
are ignored by the PHY.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of
carrier. This is when squelch is passed in 10Mbps mode, and when two non-contiguous zeroes in 10 bits are detected in
100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
August 2010
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RMII
Signal Name
REF_CLK
TXEN
TXD[1:0]
CRS_DV
RXD[1:0]
RXER
Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, 1 pin for the 50MHz reference clock).
10Mbps and 100Mbps data rates are supported at both half and full duplex.
Data transmission and reception are independent and belong to separate signal groups.
Transmit data and receive data are each 2-bit wide, a dibit.
Direction
(with respect to PHY,
KSZ8021/31RNL signal)
Output (25MHz Clock Mode) /
<no connect> (50MHz Clock
Mode)
Input
Input
Output
Output
Output
Table 1. RMII Signal Description
Output
Input
Input
Direction
(with respect to
MAC)
Input /
Input or <no connect>
Output
Input, or (not
required)
15
Description
Synchronous 50MHz reference clock for
receive, transmit and control interface
Transmit Enable
Transmit Data [1:0]
Carrier Sense/Receive Data Valid
Receive Data [1:0]
Receive Error
KSZ8021RNL / KSZ8031RNL
M9999-082710-1.0