ksz8021rnli Micrel Semiconductor, ksz8021rnli Datasheet - Page 22

• Manufacturer Part Number: ksz8021rnli
• Description: 10base-t/100base-tx Phy With Rmii Support
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
NAND Tree I/O Testing
The following procedure can be used to check for faults on the KSZ8021/31RNL digital I/O pin connections to the board:
Each KSZ8021/31RNL NAND tree input pin must cause the TXD1 output pin to toggle high-to-low or low-to-high to
indicate a good connection. If the TXD1 pin fails to toggle when the KSZ8021/31RNL input pin toggles from high to low,
then the input pin has a fault.
Power Management
The KSZ8021/31RNL offers the following power management modes:
Power Saving Mode
Power Saving Mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled by
writing a one to register 1Fh, bit [10], and is in effect when auto-negotiation mode is enabled and cable is disconnected
(no link).
In this mode, the KSZ8021/31RNL turns off all transceiver blocks, except for transmitter, energy detect and PLL circuits.
By default, Power Saving Mode is disabled after power-up.
Energy Detect Power Down Mode
Energy Detect Power Down (EDPD) Mode is used to further reduce the transceiver power consumption when the cable is
un-plugged. It is enabled by writing a zero to register 18h, bit [11], and is in effect when auto-negotiation mode is enabled
and cable is disconnected (no link).
EDPD Mode works in conjunction with PLL off (set by writing a one to register 10h, bit [4] to turn PLL off automatically in
EDPD Mode) to turn off all KSZ8021/31RNL transceiver blocks, except for transmitter and energy detect circuits.
Further power consumption is achieved by extending the time interval in between transmissions of link pulses to check for
the presence of a link partner. The periodic transmission of link pulses is needed to ensure two link partners in the same
low power state and with auto MDI/MDI-X disabled can wake up when the cable is connected between them.
By default, Energy Detect Power Down Mode is disabled after power-up.
Power Down Mode
Power Down Mode is used to power down the KSZ8021/31RNL device when it is not in use after power-up. It is enabled
by writing a one to register 0h, bit [11].
In this mode, the KSZ8021/31RNL disables all internal functions, except for the MII management interface. The
KSZ8021/31RNL exits (disables) Power Down Mode after register 0h, bit [11] is set back to zero.
August 2010
1. Enable NAND tree mode by setting register 16h, bit [5] to ‘1’.
2. Use board logic to drive all KSZ8021/31RNL NAND tree input pins high.
3. Use board logic to drive each NAND tree input pin, per KSZ8021/31RNL NAND Tree pin order, as follow:
a. Toggle the first pin (MDIO) from high to low, and verify the TXD1 pin switch from low to high to indicate
b. Leave the first pin (MDIO) low.
c. Toggle the second pin (MDC) from high to low, and verify the TXD1 pin switch from high to low to indicate
d. Leave the first pin (MDIO) and the second pin (MDC) low.
e. Toggle the third pin from high to low, and verify the TXD1 pin switch from low to high to indicate that the
f.
that the first pin is connected properly.
that the second pin is connected properly.
third pin is connected properly.
Continue with this sequence until all KSZ8021/31RNL NAND tree input pins have been toggled.
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KSZ8021RNL / KSZ8031RNL
M9999-082710-1.0