ml67q5003 Oki Semiconductor, ml67q5003 Datasheet - Page 12

• Manufacturer Part Number: ml67q5003
• Description: 32-bit Arm -based General Purpose Microcontrollers Ml675k Seriesml675001/ml67q5002/ml67q5003 32-bit Arm -based General Purpose Microcontrollers
• Manufacturer: Oki Semiconductor

ML675001/ML67Q5002/ML67Q5003
Pin Descriptions
12
System
RESET_N
BSEL[1:0]
CLKMD[1:0]
OSC0
OSC1_N
CKO
CKOE_N
JTAG Interface
TCK
TMS
nTRST
TDI
TDO
General-purpose I/O Interface
PIOA[7:0]
PIOB[7:0]
PIOC[7:0]
PIOD[7:0]
PIOE[9:0]
External Bus Interface (Global)
XA[23:19]
XA[18:0]
XD[15:0]
External Bus Interface (ROM, SRAM and I/O)
XROMCS_N
XRAMCS_N
XIOCS_N[0]
XIOCS_N[1]
XIOCS_N[2]
• Oki Semiconductor
Pin Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
April 2004, Rev 2.0
Reset input
Boot device select signal.
The selected device is mapped to BANK0 (0x0000_0000 - 0x07FF_FFFF) after reset.
Clock mode inputs. Normally connected to GND.
Crystal oscillator connection or external clock input.
If used, connect a crystal oscillator (5 MHz to 14 MHz) to OSC0 and OSC1_N.
It is also possible to input a direct clock (5 MHz, 20 MHz to 56 MHz).
Oscillation output pin.
When not using a crystal oscillator, leave this pin unconnected.
Clock out.
Clock out enable.
Debugging pin. Normally connect to ground level.
Debugging pin. Normally drive at High level.
Debugging pin. Normally connect to ground level.
Debugging pin. Normally drive at High level.
Debugging pin. Normally leave open.
General-purpose port.
Not available for use as port pins when secondary functions are in use.
General-purpose port.
Not available for use as port pins when secondary functions are in use.
General-purpose port.
Not available for use as port pins when secondary functions are in use.
General-purpose port.
Not available for use as port pins when secondary functions are in use.
Note that enabling the DRAM controller by asserting the DRAME_N inputs permanently con-
figures PIOD[7:0] for their secondary functions, making them unavailable for use as port
pins.
General-purpose port. Not available for use as port pins when secondary functions are in
use.
Address bus to external RAM, external ROM, external I/O banks, and external DRAM. After
a reset, these pins are configured for their primary function PIOC[6:2].
Address bus to external RAM, external ROM, external I/O banks, and external DRAM.
Data bus to external RAM, external ROM, external I/O banks, and external DRAM.
ROM bank chip select.
SRAM bank chip select.
I/O chip select 0.
I/O chip select 1.
I/O chip select 2.
BSEL[1]
H
L
L
BSEL[0]
H
L
*
Internal Flash (External ROM for ML675001)
External ROM
Boot ROM (* = don’t care)
Description
Boot device
Secondary
Secondary
Primary/
Primary
Primary
Primary
Primary
Primary
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Logic
–
–
–
–