ml67q5003 Oki Semiconductor, ml67q5003 Datasheet - Page 13

• Manufacturer Part Number: ml67q5003
• Description: 32-bit Arm -based General Purpose Microcontrollers Ml675k Seriesml675001/ml67q5002/ml67q5003 32-bit Arm -based General Purpose Microcontrollers
• Manufacturer: Oki Semiconductor

Pin Descriptions (Continued)
XIOCS_N[3]
XOE_N
XWE_N
XBS_N[1:0]
XBWE_N[0]
XBWE_N[1]
XWR
XWAIT
External Bus Interface (EDO-DRAM and SDRAM)
XRAS_N
XCAS_N
XSDCLK
XSDCKE
XSDCS_N
XDQM[1]/
XCAS_N[1]
XDQM[0]/
XCAS_N[0]
DMA Interface
DREQ[0]
DREQCLR[0]
TCOUT[0]
DREQ[1]
DREQCLR[1]
TCOUT[1]
UART Interface
SIN
SOUT
CTS
DSR
DCD
DTR
RTS
Pin Name
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I/O chip select 3.
Output enable/ Read enable.
Write enable.
Byte select: XBS_N[1] is for MSB, XBS_N[0] is for LSB.
LSB Write enable.
MSB Write enable.
Data transfer direction for external bus, used when connecting to Motorola I/O devices. This
represent the secondary function of pin PIOC[7].
L = read, H = write. Available for I/O bank 0/1
External I/O bank 0/1/2/3 WAIT signal.
This pin permits access to devices slower than register settings.
Row address strobe. Used for both EDO DRAM and SDRAM.
Column address strobe signal (SDRAM).
SDRAM clock (same frequency as internal system clock).
Clock enable (SDRAM).
Chip select (SDRAM).
Connected to SDRAM: DQM (MSB).
Connected to EDO-DRAM: column address strobe signal (MSB).
Connected to SDRAM: DQM (LSB).
Connected to EDO-DRAM: column address strobe signal (LSB).
Channel 0 DMA request signal. Used then DMA controller is configured for DREQ type.
Channel 0 DREQ signal clear request. The DMA device responds to the assertion of this sig-
nal by negating DREQ.
This signal is driven by the MCU and indicates to the Channel 0 DMA device that the last
transfer of the DMA operation has started.
Channel 1 DMA request signal. Used then DMA controller is configured for DREQ type.
Channel 1 DREQ signal clear request. The DMA device responds to the assertion of this sig-
nal by negating DREQ.
This signal is driven by the MCU and indicates to the Channel 1 DMA device that the last
transfer of the DMA operation has started.
UART receive signal.
UART transmit signal.
Clear To Send.
Indicates that modem or data set is ready to transfer data. Bit 4 in the modem status reg-
ister reflects this input.
Data Set Ready.
Indicates that modem or data set is ready to establish a communications link with UART.
Bit 5 in the modem status register reflects this input.
Data Carrier Detect.
Indicates that modem or data set has detected data carrier signal. Bit 7 in the modem status
register reflects this input.
Data Terminal Ready.
Indicates that UART is ready to establish a communications link with the modem or data set.
Bit 0 in the modem control register controls this output.
Request To Send.
indicates that UART is ready to transfer data to modem or data set. Bit 1 in the modem con-
trol register controls this output.
Description
April 2004, Rev 2.0
ML675001/ML67Q5002/ML67Q5003
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Primary/
–
–
–
–
–
–
Oki Semiconductor • 13
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Logic
–
–
–