ml67q5003 Oki Semiconductor, ml67q5003 Datasheet - Page 3

• Manufacturer Part Number: ml67q5003
• Description: 32-bit Arm -based General Purpose Microcontrollers Ml675k Seriesml675001/ml67q5002/ml67q5003 32-bit Arm -based General Purpose Microcontrollers
• Manufacturer: Oki Semiconductor

Functional Description
CPU
Built-in Memory
Interrupt Controller
Fast interrupt request (FIQ) and interrupt request (IRQ) are employed as inter-
rupt input signals. The interrupt controller controls these interrupt signals
going to ARM core.
1. Interrupt sources
2. Interrupt priority level
3. External interrupt pin input
Timers
The MCU contains seven 16-bit reload timers. Of these, 1 timer is used as sys-
tem timer for operating system. The other 6 timers are used by application
software.
1. System timer: 1 channel
2. Application timer: six channels
CPU core:
Operating
frequency:
Byte Ordering:
Instructions:
General register
bank:
Built-in barrel
shifter:
Multiplier:
Built-in debug
function:
FLASH ROM:
SRAM:
Cache memory:
- FIQ: One external source (external pin: EFIQ_N)
- IRQ: Total of 27 sources. 23 internal sources, and 4 external sources
- Configurable, 8-level priority for each source
- EXINT[3:0] can be set as Level or Edge sensing
- Configurable High or Low when Level sensing. Configurable Rise or Fall-
- EFIQ_N is set as Falling edge triggering.
- 16-bit auto reload timer: Used as system timer for OS. Interrupt request
- 16-bit auto reload timer. Interrupt request by compare match.
(External pins EXINT[3:0])
ing edge triggering when Edge sensing.
by timer overflow.
ARM7TDMI
1 MHz to 60 MHz (max)
Little endian.
ARM instruction (32-bit length) and Thumb instruction
(16-bit length) can be mixed
31 registers x 32 bits
ALU and barrel shift operations can be executed by one
instruction.
32 bits x 8 bits (Modified Booth’s Algorithm)
JTAG interface, break point register
ML675001: ROM-less version
ML67Q5002: 256 Kbytes (128K x 16 bits)
ML67Q5003: 512 Kbytes (256K x 16 bits)
Access timing of this FLASH memory is configured by the
ROM bank control register of the external memory
controller.
32KB (8K x 32bits)
Connected to processor bus (1-cycle read, 2-cycle write)
8K unified memory with 4-way set-associative
Watch Dog Timer
Functions as an interval timer or a watch dog timer.
• 16-bit timer
• Watch dog timer or interval timer mode can be selected
• Interrupt reset generation
• Maximum period: longer than 200 msec
Serial Interface
The ML675001/Q5002/Q5003 contains four serial interfaces.
1. SIO without FIFO: 1 channel
2. UART with 16-byte FIFO: 1 channel
3. Synchronous serial interface: 1 channel
4. I
- One shot, interval
- Clock can be independently set for each channel
This is the serial port which performs data transmission, taking a synchro-
nization per character. Selection of various parameters, such as addition
of data length, a stop bit, and a parity bit, is possible.
- Asynchronous full duplex operation
- Sampling Rate = Baud rate x 16 samples
- Character Length: 7, 8 bit
- Stop Bit Length: 1, 2 bit
- Parity: Even, Odd, none
- Error Detection: Parity, Framing, Over run
- Loop Back Function: ON/OFF, Parity, framing, Over run Compulsive
- Baud Rate Generation: Exclusive baud rate generator built-in (8-bit
- Internal-Baud-Rate-Clock-Stop at the Time of HALT Mode.
Features 16-byte FIFO in both send and receive. Uses the industry stan-
dard 16550A ACE (Asynchronous Communication Element).
- Asynchronous full duplex operation
- Reporting function for all status
- 16 Byte transmission and reception FIFO
- Transmission, reception, interrupt of line status Data set and Indepen-
- Modem control signals: CTS, DCD, DSR, DTR, RI and RTS
- Data length: 5, 6, 7, or 8 bits
- Stop bit length: 1, 1.5, or 2 bits
- parity: Even, Odd, or none
- Error Detection: Parity, Framing, Overrun
- Baud Rate Generation: Exclusive baud rate generator built-in
Clock-synchronous 8-bit serial port
- selectable 1/8, 1/16 or 1/32 of the system clock frequency.
- LSB First or MSB First.
- Master / Slave Mode
- Transceiver buffer empty interrupt
- Loopback test function
Based on the I
- Communication mode: Master transmitter /master receiver
- Transmission Speed: 100 kbps (Standard mode) / 400 kbps (Fast mode)
- Addressing format: 7 bit / 10 bit
- Data buffer: 1 Byte (1step)
- Communication Voltage: 2.7 V to 3.3 V
2
C: 1 channel
addition
counter) Independent from a bus clock
dent FIFO control.
2
C Bus specification. Operates as a single master device.
April 2004, Rev 2.0
ML675001/ML67Q5002/ML67Q5003
Oki Semiconductor • 3