ml67q5003 Oki Semiconductor, ml67q5003 Datasheet - Page 4

• Manufacturer Part Number: ml67q5003
• Description: 32-bit Arm -based General Purpose Microcontrollers Ml675k Seriesml675001/ml67q5002/ml67q5003 32-bit Arm -based General Purpose Microcontrollers
• Manufacturer: Oki Semiconductor

ML675001/ML67Q5002/ML67Q5003
Direct Memory Access Controller
Two DMA channels that transfer data between:
• Memory and memory
• I/O and memory
• I/O and I/O.
4
1. Number of
2. Channel priority
3. Maximum number
4. Data transfer size: Byte (8 bits), Half-word (16 bits), Word (32 bits)
5. Bus request
6. DMA transfer
7. Interrupt request:
• Oki Semiconductor
channels:
level:
of transfers:
system:
request:
2 channels
Fixed mode:
Roundrobin:
65,536 (64K times).
Cycle steal
mode:
Burst mode:
Software
request:
External
request:
Interrupt request is generated in CPU after the end
of DMA transfer for the set number of transfer
cycles, or after the occurrence of an error.
Interrupt request signal is output separately for
each channel.
Interrupt request signal output can be masked for
each channel.
April 2004, Rev 2.0
Channel priority level is always
fixed (channel 0 >1).
Priority level of the channel
requested for transfer is kept
lowest.
Bus request signal is asserted for
each DMA transfer cycle.
Bus request signal is asserted until
all transfers of transfer cycles are
complete.
By setting the software transfer
request bit inside the DMAC, the
CPU starts DMA transfer.
DMA transfer is started by exter-
nal request allocated to each
channel.
Controls access of externally connected devices such as ROM (FLASH), SRAM,
SDRAM (EDO DRAM) and I/O devices.
1. ROM (FLASH) access function: 1 bank
2. SRAM access function: 1 bank
3. DRAM access function: 1 bank
4. External I/O access function: 2 banks
External Memory Controller
GPIO
42-bit parallel port (four 8-bit ports and one 10-bit port).
1. Input/output selectable at bit level.
2. Each bit can be used as an interrupt source.
3. Interrupt mask and interrupt mode (level) can be set for all bits.
4. The ports are configured as inputs immediately after reset.
5. Primary/secondary function of each port can be set independently.
Supports 16-bit devices
Supports FLASH memory: Byte write (can be written only by IF equivalent
to SRAM). In ML67Q5002/5003, control internal FLASH access.
Configurable access timing.
Supports 16-bit devices
Supports asynchronous SRAM
Configurable access timing.
Supports 16-bit devices
Supports EDO/SDRAM: Simultaneous connections to EDO-DRAM and
SDRAM cannot be made.
Configurable access timing.
Supports 8-bit/16-bit access: Independent configuration for each bank.
Each bank has two chip selects: XIOCS_N[3:0].
Supports external wait input: XWAIT
Access timing configurable for each bank independently.
PIOA[7:0]
PIOB[7:0]
PIOC[7:0]
PIOD[7:0]
PIOE[9:0]
Combination port
Combination port
Combination port
Combination port
Combination port
UART
DMAC, SIO (µPLAT-7B)
PWM, XA[23:19], XWR
DRAM control signals etc.
SSIO, I
2
C, External interrupt signal