ml671000 Oki Semiconductor, ml671000 Datasheet
ml671000
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ml671000 Summary of contents
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... Semiconductor ML671000 OKI’s CMOS 32-Bit Single-Chip Microcontroller with Built-in USB Device Controller GENERAL DESCRIPTION The ML671000 is a high-performance CMOS 32-bit microcontroller combining a RISC based, 32-bit CPU core - TM the ARM7TDMI - with USB device controller, memory and peripherals. The built-in USB device controller which is based on USB1.1 Full-speed (12 Mbps) makes interface with PCs or other devices by USB ...
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... Digital still camera, Printer, Terminal Adapter for PC peripherals and Communication terminals. 22 (13 internal , 9 external ) 8 levels ROM, RAM, I/O 2 banks; DRAM Access wait control parameters for each bank. Standby modes: HALT and STOP modes Clock gears: Selection of 1/2 OSC, 1/1 OSC, OSC 2 4 FEDL671000-02 ML671000 2 banks 2/25 ...
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... Core Address Bus Internal Bus/External Memory Controller Interrupt Controller Time Base Generator Flexible Timer/ Auto-reload Timer (two each) USB Device Controller PLL I/O Port Asterisks indicate pins with secondary functions. FEDL671000-02 ML671000 P0[7:0]/XA[23:16] XA[15:1] XA0/nLB XD[15:0] nR/W nCS0 nRD nWRE/nWRL P1.7/nXWAIT P1.6/nCS1 P1.5/nHB/nWRH P1.4/nRAS1 P1.3/nWH/nCASH P1 ...
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... P6.4/DACK0 116 P6.5/DACK1 117 P6.6/nBREQ 118 P6.7/nBACK 119 120 DD 121 P7.0 122 P7.1 123 P7.2 P7.3 124 125 P7.4 126 P7.5 P7.6 127 128 P7.7 128-Pin Plastic QFP FEDL671000-02 ML671000 64 OSCV SS 63 OSC1 62 OSC0 61 OSCV DD 60 nEA 59 DBSEL P1.7/nXWAIT 53 P1.6/nCS1 52 P1.5/nHB/nWRH 51 P1.4/nRAS1 50 P1 ...
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... Bit 2 of port 1 Secondary Bank 2 row address strobe signal Primary Bit 1 of port 1 Bank 2/3 column address strobe or lower byte column address strobe Secondary signal Primary Bit 0 of port 1 Secondary Bank 2/3 lower byte write enable or write enable signal FEDL671000-02 ML671000 Description ...
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... Receive data input pin for UART/synchronous serial port Primary Bit 3 of port 4 Secondary Transmit clock I/O pin for UART/synchronous serial port Primary Bit 2 of port 4 Secondary Receive clock I/O pin for UART/synchronous serial port — Bit 1 of port 4 — Bit 0 of port 4 FEDL671000-02 ML671000 Description 6/25 ...
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... GND. — This pin sets the test and debug modes for this LSI device. Normally connected to GND. — Power supply pin. Connect all V — Ground pin. Connect all V FEDL671000-02 ML671000 Description . To set an 8-bit bus DD pins to the power supply. DD pins to GND. SS 7/25 ...
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... Modem control signals: CTS, DSR, DCD, DTR, RTS and RI - Built-in dedicated baud rate generator - Data length: bits - Stop bit bits - Parity: odd, even, or none - Detection of receive errors: parity error, framing error, overrun error, or data error of break interrupt FEDL671000-02 ML671000 8/25 ...
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... Transfer data size: - Maximum transferring: - Addressing modes: - Bus modes: - Supports transfer requests from nDREQ[0:1] pins, internal peripheral devices and software. - Generates transfer complete interrupt requests when transfer is completed bits 65536 times single or dual address mode cycle-steal or burst mode FEDL671000-02 ML671000 9/25 ...
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... It offers a choice of divider ratio for adjusting operating clock frequency to match the load processing. When using PLL: 2 Not using PLL: f, f/2, f/4, f/8 FIFO contents 1 (transmit) Control 1 (receive) Bulk, interrupt 1 (transmit-receive) Bulk, interrupt, isochronous 2 (transmit-receive) 2 (transmit-receive) Bulk, interrupt, isochronous f, f, f/2 FEDL671000-02 ML671000 Transfer mode f = input clock frequency 10/25 ...
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... Hz DDH 3 — Input frequency Operating frequency ( MHz MHz Input frequency Operating frequency ( MHz MHz FEDL671000-02 ML671000 Rated value Unit 0.3 to +4 –55 to 150 C (GND = 0 V) Min. Typ. Max. Unit 3 ...
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... I C — — — — IO (*3) — I DDS (*4) — I — DDH MHz C No load I — 3.3 V and FEDL671000-02 ML671000 Typ. (*1) Max. Unit — 5.5 — 0 0.8 — — 0.2 — — — 0.4 — 1.0 (*2) — 1.0 (*2) ...
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... V EXC EXC t 15 EXCH t 15 EXCL t — — — — — — EXR t — — EXF FEDL671000-02 ML671000 Typ. (*1) Max. Unit — 2.5 V 2.0 3.6 0.3 — Typ. Max. Unit — 24 MHz — 250 — — ns — — — 24 MHz — ...
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... XWAITH t HBD t CSD WRD t RDD t R/WD t RASD t CASD t WED t BREQS t BREQH t BACKD t XHD FEDL671000-02 ML671000 Typ. Max. Unit — — ns — — — — — — — ns — — — — — 1/4 f MHz C — — — — — — ...
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... Semiconductor TIMING DIAGRAMS Clock Timing CLKOUT External clock Input EXC t t EXCH EXCL FEDL671000-02 ML671000 EXR EXF 15/25 ...
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... Semiconductor Control Signal Timing nRST nEFIQ, nEIR TMIN TMCLK TXC, RXC TXD RXD RSTW1 RSTW2 EFIQW EIRW t TMINW t TMCLKW t t SCLKH SCLKL t TXDH t RXDS FEDL671000-02 ML671000 t TMCLKW t RXDH 16/25 ...
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... Semiconductor DMA Timing CLKOUT nDREQ0, nDREQ1 DACK0, DACK1 nXWAIT Signal Input Timing CLKOUT nXWAIT t t REQS REQH t XWAITS FEDL671000-02 ML671000 t DACKD t XWAITH 17/25 ...
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... Semiconductor External Bus Release Timing CLKOUT nBREQ nBACK XA, XD Control signals t XWAITS t BACKD t XHD FEDL671000-02 ML671000 t XWAITH t BACKD t XHD 18/25 ...
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... Semiconductor External Bus Timing Bank 0, 1 write cycle CLKOUT XA[23:1] nLB/XA0 nHB nCS[1:0] nWRE nWRH, nWRL nR/W XD Write Cycle t XAD t HBD t CSD t WRD t R/WD t XDOD FEDL671000-02 ML671000 t WRD t XDOH 19/25 ...
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... Semiconductor Bank 0, 1 read cycle CLKOUT XA[23:1] nLB/XA0 nHB nCS[1:0] nRD nR/W XD Read Cycle t XAD t HBD t CSD t t RDD RDD t R/ XDIS XDIH FEDL671000-02 ML671000 20/25 ...
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... Semiconductor Bank 2, 3 write cycle CLKOUT XA[23:1] nLB/XA0 nRAS[1:0] nCAS[1:0] nWE nWH, nWL XD nR/W W rite Cycle t XAD t R ASD FEDL671000-02 ML671000 t R ASD ASD C ASD 21/25 ...
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... Semiconductor Bank 2, 3 read cycle CLKOUT XA[23:1] nLB/XA0 nRAS[1:0] nCAS[1:0] XD nR/W Read Cycle t XAD t R ASD FEDL671000-02 ML671000 t R ASD ASD C ASD 22/25 ...
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... Semiconductor CAS before RAS (CBR) refresh CLKOUT nRAS nCAS Self-refresh CLKOUT nRAS nCAS RASD FEDL671000-02 ML671000 23/25 ...
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... The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). FEDL671000-02 ML671000 (Unit: mm) 24/25 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. FEDL671000-02 Copyright 2001 Oki Electric Industry Co., Ltd. ML671000 25/25 ...