ml671000 Oki Semiconductor, ml671000 Datasheet - Page 5

• Manufacturer Part Number: ml671000
• Description: Oki S Mcus - Ml671000oki S Cmos 32-bit Single-chip Microcontroller With Built-in Usb Device Controller
• Manufacturer: Oki Semiconductor

PIN DESCRIPTION (1)
1 Semiconductor
Classification
Address Bus
Data Bus
Bus Control
Clock Control
I/O Ports
XA15 to XA1
nLB/XA0
XD15 to XD0
nCS0
nRD
nR/W
nWRE/nWRL
OSC0
OSC1
CLKOUT
PLLEN
OSCV
OSCV
P0.7/XA23
P0.6/XA22
P0.5/XA21
P0.4/XA20
P0.3/XA19
P0.2/XA18
P0.1/XA17
P0.0/XA16
P1.7/nXWAIT
P1.6/nCS1
P1.5/nHB/
nWRH
P1.4/nRAS1
P1.3/
nWH/nCASH
P1.2/nRAS0
P1.1/
nCAS/nCASL
P1.0/
nWL/nWE
Pin Name
DD
SS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Function
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
—
—
—
—
—
—
—
—
—
—
—
—
—
External address bus bits 15 to 1
Bank 0/1 lower byte select or external address bus bit 0
External data bus
Bank 0 chip select signal
Bank 0/1 read enable signal
Read strobe signal
Bank 0/1 write enable or lower byte write enable signal
Connection pin for crystal oscillator or ceramic resonator
If an external clock used, input the clock signal to this pin.
Connection pin for crystal oscillator or ceramic resonator
If an external clock used, leave this pin open (unconnected).
Internal system clock output
Enable pin for internal PLL. If PLL is to be used, connect this pin to V
Power supply pin for internal oscillator circuit and PLL. Connect to V
Power supply pin for internal oscillator circuit and PLL. Connect to
GND.
Bit 7 of port 0
Bit 23 of external address bus
Bit 6 of port 0
Bit 22 of external address bus
Bit 5 of port 0
Bit 21 of external address bus
Bit 4 of port 0
Bit 20 of external address bus
Bit 3 of port 0
Bit 19 of external address bus
Bit 2 of port 0
Bit 18 of external address bus
Bit 1 of port 0
Bit 17 of external address bus
Bit 0 of port 0
Bit 16 of external address bus
Bit 7 of port 1
External wait cycle insert input
Bit 6 of port 1
Bank 1 chip select signal
Bit 5 of port 1
Bank 0/1 upper byte select or upper byte write enable signal
Bit 4 of port 1
Bank 3 row address strobe signal
Bit 3 of port 1
Bank 2/3 upper byte column address strobe signal.
Bit 2 of port 1
Bank 2 row address strobe signal
Bit 1 of port 1
Bank 2/3 column address strobe or lower byte column address strobe
signal
Bit 0 of port 1
Bank 2/3 lower byte write enable or write enable signal
Description
FEDL671000-02
ML671000
5/25
DD
DD
.
.