ml671000 Oki Semiconductor, ml671000 Datasheet - Page 9

• Manufacturer Part Number: ml671000
• Description: Oki S Mcus - Ml671000oki S Cmos 32-bit Single-chip Microcontroller With Built-in Usb Device Controller
• Manufacturer: Oki Semiconductor

UART/Synchronous Serial Port
Interrupt Controller
Direct Memory Access (DMA) Controller
1 Semiconductor
The UART/synchronous serial port is a serial port that operates in two communication modes, the UART
mode and synchronous mode. In the UART mode, characters units are synchronized according to the
controlled start bit and stop bit, and data is transferred. In the synchronous mode, the data transfer is
synchronized to the controlled shift clock.
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The interrupt controller manages interrupt requests from 9 external sources and 13 internal sources, and passes
them on to the CPU as interrupt request (IRQ) or fast interrupt request (FIQ) exception requests. An interrupt
level can be set for each interrupt and priority can be controlled.
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The direct memory access (DMA) controller is used instead of the CPU to transfer data between internal
memory, internal peripherals, external memory and memory mapped external devices.
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Built-in dedicated baud rate generator
Data length:7 or 8 bits
Stop bit:
Parity:
Detection of receive errors: parity error, framing error, and overrun error
(only overrun error in the synchronous mode)
Full-duplex operation
Supports 9 external interrupt sources from nEFIQ and nEIR [7:0] pins and 13 internal interrupt sources
from internal peripherals such as the USB device controller and the timers.
To simplify the control of interrupt priority, 8 interrupt levels can be set for each interrupt source.
The interrupt controller assigns a unique interrupt number to each interrupt source to permit rapid
branching to the appropriate routine.
Built-in 2 channels
Supports 64MB address area
Transfer data size:
Maximum transferring:
Addressing modes:
Bus modes:
Supports transfer requests from nDREQ[0:1] pins, internal peripheral devices and software.
Generates transfer complete interrupt requests when transfer is completed.
1 or 2 bits (UART mode only)
even or odd parity (none in the synchronous mode)
8 or 16 bits
65536 times
single or dual address mode
cycle-steal or burst mode
FEDL671000-02
ML671000
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