mc68hc908bd48 Freescale Semiconductor, Inc, mc68hc908bd48 Datasheet - Page 142

• Manufacturer Part Number: mc68hc908bd48
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module (TIM)
Data Sheet
142
Figure 10-6. TIM Channel Status and Control Registers (TSC0:TSC1)
Address:
Address:
CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
Reset:
Reset:
Read:
Write:
Read:
Write:
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE=1), clear
CHxF by reading the TIM channel x status and control register with
CHxF set and then writing a logic zero to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic zero to CHxF has no effect. Therefore, an interrupt request
cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic one to CHxF has no effect.
This read/write bit enables TIM CPU interrupt service requests on
channel x. Reset clears the CHxIE bit.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
$0010
$0013
CH0F
CH1F
Bit 7
Bit 7
0
0
0
0
Timer Interface Module (TIM)
CH0IE
CH1IE
= Unimplemented
TSC0
TSC1
6
0
6
0
MS0B
5
0
5
0
0
MS0A
MS1A
4
0
4
0
ELS0B
ELS1B
3
0
3
0
MC68HC908BD48
ELS0A
ELS1A
Freescale Semiconductor
2
0
2
0
TOV0
TOV1
1
0
1
0
—
CH0MAX
CH1MAX
Rev. 2.1
Bit 0
Bit 0
0
0