mc68hc908bd48 Freescale Semiconductor, Inc, mc68hc908bd48 Datasheet - Page 255
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mc68hc908bd48
Manufacturer Part Number
mc68hc908bd48
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC908BD48.pdf
(288 pages)
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18.6 IRQ Module During Break Interrupts
18.7 IRQ Status and Control Register
MC68HC908BD48
Freescale Semiconductor
NOTE:
—
Rev. 2.1
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear the latch during the break state.
Module
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect CPU interrupt flags during the break state, write a logic 0 to
the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK
bit in the IRQ status and control register during the break state has no
effect on the IRQ interrupt flags.
The IRQ status and control register (INTSCR) controls and monitors
operation of the IRQ module. The INTSCR:
•
•
•
•
Shows the state of the IRQ flag
Clears the IRQ latch
Masks IRQ interrupt request
Controls triggering sensitivity of the IRQ interrupt pin
(BRK).
External Interrupt (IRQ)
See Section 20. Break
External Interrupt (IRQ)
Data Sheet
255
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