mc68hc912bc32 Freescale Semiconductor, Inc, mc68hc912bc32 Datasheet - Page 263

• Manufacturer Part Number: mc68hc912bc32
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

SFTRES — Soft-Reset Bit
16.12.2 msCAN12 Module Control Register 1
LOOPB — Loop Back Self-Test Mode Bit
WUPM — Wakeup Mode Flag
Freescale Semiconductor
When this bit is set by the CPU, the msCAN12 immediately enters the soft-reset state. Any on-going
transmission or reception is aborted and synchronization to the bus is lost.
These registers will go into and stay in the same state as out of hard reset: CMCR0, CRFLG, CRIER,
CTFLG, and CTCR.
Registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0–CIDAR7, and CIDMR0–CIDMR7 can be written
only by the CPU when the msCAN12 is in soft-reset state. The values of the error counters are not
affected by soft reset.
When this bit is cleared by the CPU, the msCAN12 will try to synchronize to the CAN bus. For example,
if the msCAN12 is not in bus-off state, it will be synchronized after 11 recessive bits on the bus; if the
msCAN12 is in bus-off state, it continues to wait for 128 occurrences of 11 recessive bits.
Clearing SFTRES and writing to other bits in CMCR0 must be in separate instructions.
When this bit is set, the msCAN12 performs an internal loop back which can be used for self-test
operation. The bit stream output of the transmitter is fed back to the receiver. The RxCAN input pin is
ignored and the TxCAN output goes to the recessive state (1). In this state the msCAN12 ignores the
bit sent during the ACK slot of the CAN frame acknowledge field to ensure proper reception of its own
message. Both transmit and receive interrupts are generated.
This flag defines whether the integrated low-pass filter is applied to protect the msCAN12 from
spurious wakeups. See
0 = Normal operation
1 = msCAN12 in soft-reset state
0 = Normal operation
1 = Activate loop back self-test mode
0 = msCAN12 will wake up the CPU after any recessive-to- dominant edge on the CAN bus.
1 = msCAN12 will wake up the CPU only in the case of a dominant pulse on the bus which has a
length of approximately t
Address: $0101
The ACK bit is added to the CAN frame by the protocol. For more
information on the CAN frame and the ACK bit, refer to the Bosch CAN 2.0
specification.
Reset:
Read:
Write:
Figure 16-17. msCAN12 Module Control Register 1 (CMCR1)
Bit 7
0
0
16.7.4 Programmable Wakeup
= Unimplemented
6
0
0
M68HC12B Family Data Sheet, Rev. 9.1
WUP
.
5
0
0
NOTE
4
0
0
Function.
3
0
0
Programmer’s Model of Control Registers
LOOPB
2
0
WUPM
1
0
CLKSRC
Bit 0
0
263