mc68hc912bc32 Freescale Semiconductor, Inc, mc68hc912bc32 Datasheet - Page 293

• Manufacturer Part Number: mc68hc912bc32
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

18.3.3 BDM Commands
All BDM command opcodes are eight bits long and can be followed by an address and/or data, as
indicated by the instruction. These commands do not require the CPU to be in active BDM for execution.
The host controller must wait 150 cycles for a non-intrusive BDM command to execute before another
command can be sent. This delay includes 128 cycles for the maximum delay for a dead cycle. For data
read commands, the host must insert this delay between sending the address and attempting to read the
data.
BDM logic retains control of the internal buses until a read or write is completed. If an operation can be
completed in a single cycle, it does not intrude on normal CPU operation. However, if an operation
requires multiple cycles, CPU clocks are frozen until the operation is complete.
The two types of BDM commands are:
Hardware commands allow target system memory to be read or written. Target system memory includes
all memory that is accessible by the CPU12 including on-chip RAM, EEPROM, on-chip I/O and control
registers, and external memory connected to the target HC12 MCU. Hardware commands are
implemented in hardware logic and do not require the HC12 MCU to be in BDM mode for execution. The
control logic watches the CPU12 buses to find a free bus cycle to execute the command so that the
background access does not disturb the running application programs. If a free cycle is not found
within 128 E-clock cycles, the CPU12 is momentarily frozen so the control logic can steal a cycle. Refer
to
Freescale Semiconductor
Table 18-2
READ_BD_WORD
WRITE_BD_BYTE
•
•
READ_BD_BYTE
BACKGROUND
READ_WORD
FIRMWARE
READ_BYTE
Command
STATUS
ENABLE_
Hardware
Firmware
(1)
for commands implemented in BDM control logic.
(2)
Opcode (Hex)
EC
E4
E4
E0
E8
C4
C4
90
Table 18-2. BDM Hardware Commands
M68HC12B Family Data Sheet, Rev. 9.1
1000 0000 (out)
0000 0000 (out)
1100 0000 (out)
16-bit address
16-bit data out
16-bit address
16-bit address
16-bit data out
16-bit address
16-bit data out
16-bit address
16-bit data out
1xxx xxxx (in)
16-bit data in
FF01,
FF01,
FF01,
FF01,
None
Data
Enter background mode (if firmware enabled).
Read from memory with BDM in map (may steal cycles if
external access) data for odd address on low byte, data for even
address on high byte.
READ_BD_BYTE $FF01. Running user code. (BGND
instruction is not allowed.)
READ_BD_BYTE $FF01. BGND instruction is allowed.
READ_BD_BYTE $FF01. Background mode active (waiting for
single wire serial command).
Read from memory with BDM in map (may steal cycles if
external access) must be aligned access.
Read from memory with BDM out of map (may steal cycles if
external access) data for odd address on low byte, data for even
address on high byte.
Read from memory with BDM out of map (may steal cycles if
external access) must be aligned access.
Write to memory with BDM in map (may steal cycles if external
access) data for odd address on low byte, data for even address
on high byte.
Write byte $FF01, set the ENBDM bit. This allows execution of
commands which are implemented in firmware. Typically, read
STATUS, OR in the MSB, write the result back to STATUS.
Description
Background Debug Mode (BDM)
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