mc68hc912bc32 Freescale Semiconductor, Inc, mc68hc912bc32 Datasheet - Page 79

• Manufacturer Part Number: mc68hc912bc32
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

ESTR — E Clock Stretch Enable Bit
IVIS — Internal Visibility Bit
EBSWAI — External Bus Module Stop in Wait Bit
EME — Emulate Port E Bit
Freescale Semiconductor
ESTR determines if the E clock behaves as a simple free-running clock or as a bus control signal that
is active only for external bus cycles. ESTR is always 1 in expanded modes since it is required for
address demultiplexing and must follow stretched cycles.
Normal modes: Write once
Special modes: Write anytime
IVIS determines whether internal ADDR/DATA, R/W, and LSTRB signals can be seen on the bus
during accesses to internal locations. In special expanded narrow mode, it is possible to configure the
MCU to show internal accesses on an external 16-bit bus. The IVIS control bit must be set to 1. When
the system is configured this way, visible internal accesses are shown as if the MCU was configured
for expanded wide mode, but normal external accesses operate as if the bus in narrow mode. In normal
expanded narrow mode, internal visibility is not allowed and IVIS is ignored.
Normal modes: Write once
Special modes: Write anytime except the first time
This bit controls access to the external bus interface when in wait mode. The module delays before
shutting down in wait mode to allow for final bus activity to complete.
Normal modes: Write anytime
Special modes: Write never
Removing the registers from the map allows the user to emulate the function of these registers
externally. In single-chip mode, port E data register (PORTE) and port E data direction register (DDRE)
are always in the map regardless of the state of this bit.
Normal modes: Write once
Special modes: Write anytime except the first time
1 = E stretches high during external access cycles and low during non-visible internal accesses
0 = E never stretches (always free running)
1 = Internal bus operations visible on external bus
0 = No visibility of internal bus operations on external bus
1 = External bus shut down during wait mode
0 = External bus and registers continue functioning in wait mode.
1 = PORTE and DDRE removed from the memory map (expanded mode)
0 = PORTE and DDRE in the memory map
M68HC12B Family Data Sheet, Rev. 9.1
Mode and Resource Mapping Registers
79