mpc8360e Freescale Semiconductor, Inc, mpc8360e Datasheet - Page 18

• Manufacturer Part Number: mpc8360e
• Description: Mpc8360e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

RESET Initialization
Table 11
5.3
This section specify the limits of the AC electrical characteristics for the operation of the QE’s
communication interfaces.
Table 12
18
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Time for the device to turn off POR config signals with
respect to the assertion of HRESET
Time for the device to turn on POR config signals with
respect to the negation of HRESET
Notes:
1. t
2. t
3. POR config signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
PLL lock times
DLL lock times
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk).
2. The csb_clk is determined by the CLKIN and system PLL ratio. See
the primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of
CFG_CLKIN_DIV. See the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for more
details.
See the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for more details.
A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum.
PCI_SYNC_IN
CLKIN
provides the PLL and DLL lock times.
lists the maximal QE I/O frequencies and the minimal QE core frequency for each interface.
QE Operating Frequency Limitations
Ethernet Management:
MDC/MDIO
MII
is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode.
The settings listed below are required for correct hardware interface
operation. Each protocol by itself requires a minimal QE operating
frequency setting for meeting the performance target. Because the
performance is a complex function of all the QE settings, the user should
make use of the QE performance utility tool provided by Freescale to
validate their system.
Interface
Parameter/Condition
is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode
Table 10. RESET Initialization Timing Specifications (continued)
Table 12. QE Operating Frequency Limitations
Interface Operating
Frequency (MHz)
Table 11. PLL and DLL Lock Times
10 (max)
25 (typ)
NOTE
Bit Rate (Mbps)
Max interface
7680
Min
—
—
1
100
10
Section 22, “Clocking,”
122,880
Max
100
Min QE Operating
Frequency
—
4
20
50
1
csb_clk cycles
(MHz)
t
PCI_SYNC_IN
Unit
for more information.
ns
μs
Freescale Semiconductor
Notes
Notes
1, 3
1, 2
3