mpc8360e Freescale Semiconductor, Inc, mpc8360e Datasheet - Page 54

• Manufacturer Part Number: mpc8360e
• Description: Mpc8360e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

PCI
Figure 35
54
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Input hold from Clock
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications .
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
4. Input timings are measured at the pin.
5. In rev 2.0 silicon, due to errata, t
6. In rev 2.0 silicon, due to errata, t
Clock to output valid
Output hold from Clock
Clock to output high impedance
Input setup to Clock
Input hold from Clock
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications .
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
4. Input timings are measured at the pin.
5. In rev 2.0 silicon, due to errata, t
block)(signal)(state) (reference)(state)
example, t
relative to the PCI_SYNC_IN clock, t
symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going
to the valid (V) state.
delivered through the component pin is less than or equal to the leakage current specification.
block)(signal)(state) (reference)(state)
example, t
relative to the PCI_SYNC_IN clock, t
symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going
to the valid (V) state.
delivered through the component pin is less than or equal to the leakage current specification.
provides the AC test load for PCI.
PCIVKH
PCIVKH
Parameter
Parameter
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)
Table 47. PCI AC Timing Specifications at 66 MHz (continued)
Output
Table 48. PCI AC Timing Specifications at 33 MHz
for inputs and t
for inputs and t
PCIHOV
PCIXKH
PCIXKH
SYS
SYS
Figure 35. PCI AC Test Load
minimum is 1 ns. Please refer to PCI17 in the device errata document.
minimum is 1 ns. Please refer to PCI17 in the device errata document.
maximum is 6.6ns. Please refer to PCI21 in the device errata document.
, reference (K) going to the high (H) state or setup time. Also, t
, reference (K) going to the high (H) state or setup time. Also, t
Z
0
= 50 Ω
(first two letters of functional block)(reference)(state)(signal)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
Symbol
Symbol
t
t
t
t
t
t
PCKHOV
PCKHOX
PCKHOZ
PCIXKH
PCIVKH
PCIXKH
1
1
R
Min
Min
0.3
7.0
0.3
—
—
2
L
= 50 Ω
(first two letters of functional
(first two letters of functional
Max
Max
OV
11
14
—
—
—
—
DD
/2
Freescale Semiconductor
Unit
Unit
ns
ns
ns
ns
ns
ns
for outputs. For
for outputs. For
PCRHFV
PCRHFV
Notes
2, 4, 6
Notes
2, 4, 5
2, 3
2, 4
2
2