mpc8313e Freescale Semiconductor, Inc, mpc8313e Datasheet - Page 43

• Manufacturer Part Number: mpc8313e
• Description: Mpc8313e Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

Figure 23
Figure 24
Figure 25
Freescale Semiconductor
At recommended operating conditions (see
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols used for timing specifications herein follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design and characterization.
for inputs and t
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. Also, t
data input signals (D) went invalid (X) relative to the t
provides the AC test load for TDO and the boundary-scan outputs.
provides the JTAG clock input timing diagram.
provides the TRST timing diagram.
Table 41. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)
External Clock
(first two letters of functional block)(reference)(state)(signal)(state)
TRST
MPC8313E PowerQUICC
Parameter
JTAG
Output
Figure 23. AC Test Load for the JTAG Interface
Figure 24. JTAG Clock Input Timing Diagram
Boundary-scan data
Table
VM
t
JTKHKL
Figure 25. TRST Timing Diagram
2).
VM
Z
VM = Midpoint Voltage (NV
VM = Midpoint Voltage (NV
0
TCLK
™
t
= 50 Ω
JTG
TCLK
II Pro Processor Hardware Specifications, Rev. 0
TDO
.
VM
JTG
.
t
TRST
clock reference (K) going to the high (H) state. Note that, in general,
Symbol
t
t
JTKLOZ
JTKLDZ
JTDXKH
VM
2
for outputs. For example, t
symbolizes JTAG timing (JT) with respect to the time
(first two letters of functional block)(signal)(state) (reference)(state)
DD
DD
R
/2)
/2)
VM
L
= 50 Ω
Min
TCLK
t
2
2
JTGR
to the midpoint of the signal in question.
NV
Max
DD
19
t
9
JTGF
/2
JTDVKH
1
(continued)
symbolizes JTAG
Unit
ns
Figure
JTG
clock
17).
Notes
5, 6
JTAG
43