mpc8313e Freescale Semiconductor, Inc, mpc8313e Datasheet - Page 6

• Manufacturer Part Number: mpc8313e
• Description: Mpc8313e Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

Overview
1.10
The serial peripheral interface (SPI) allows the MPC8313E to exchange data between other PowerQUICC
family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time
clocks, A/D converters, and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface
(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an
independent baud-rate generator, and a control unit.
1.11
The MPC8313E provides an integrated four-channel DMA controller with the following features:
There are two I
devices for expansion and system development.
The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550
programming models. 16-byte FIFOs are supported for both the transmitter and the receiver.
The MPC8313E local bus controller (LBC) port allows connections with a wide variety of external DSPs
and ASICs. Three separate state machines share the same external pins and can be programmed separately
to access different types of devices. The general-purpose chip select machine (GPCM) controls accesses
to asynchronous devices using a simple handshake protocol. The three user programmable machines
(UPMs) can be programmed to interface to synchronous devices or custom ASIC interfaces. Each chip
select can be configured so that the associated chip interface can be controlled by the GPCM or UPM
controller. The FCM provides a glueless interface to parallel-bus NAND Flash E2PROM devices. The
FCM contains three basic configuration register groups–BRn, ORn, and FMR. Both may exist in the same
system. The local bus can operate at up to 66 MHz.
The MPC8313E system timers include the following features: periodic interrupt timer, real time clock,
software watchdog timer, and two general-purpose timer blocks.
6
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Allows chaining (both extended and direct) through local memory-mapped chain descriptors
(accessible by local masters).
Supports misaligned transfers
DMA Controller, Dual I
Serial Peripheral Interface (SPI)
Timers
2
C controllers. These synchronous, multi-master buses can be connected to additional
MPC8313E PowerQUICC
™
2
II Pro Processor Hardware Specifications, Rev. 0
C, DUART, Local Bus Controller, and
Freescale Semiconductor