mpc8306 Freescale Semiconductor, Inc, mpc8306 Datasheet - Page 15

• Manufacturer Part Number: mpc8306
• Description: Powerquicc Ii Pro Integrated Communications Processor Family Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

The following figure shows the input timing diagram for the DDR controller.
6.2.2
The following table provides the output AC timing specifications for the DDR2 SDRAM interfaces.
Freescale Semiconductor
At recommended operating conditions with GV
At recommended operating conditions with GV
Notes:
1. t
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t
MCK cycle time, (MCK/MCK crossing)
ADDR/CMD output setup with respect to MCK
ADDR/CMD output hold with respect to MCK
MCS output setup with respect to MCK
is captured with MDQS[n]. This should be subtracted from the total timing budget.
determined by the equation: t
value of t
CISKEW
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
MDQS[n]
MDQ[x]
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
CISKEW
MCK[n]
MCK[n]
DDR2 SDRAM Output AC Timing Specifications
.
Parameter
Parameter
Table 15. DDR2 SDRAM Input AC Timing Specifications (continued)
Table 16. DDR2 SDRAM Output AC Timing Specifications
DISKEW
=
266 MHz
266 MHz
266 MHz
266 MHz
DD
DD
Figure 4. DDR Input Timing Diagram
±
(T/4 – abs(t
of 1.8V ± 100mV.
of 1.8V ± 100mV.
t
t
MCK
DISKEW
Symbol
t
t
t
DDKHAS
DDKHAX
DDKHCS
CISKEW
t
Symbol
MCK
1
)) where T is the clock period and abs(t
D0
5.988
Min
2.5
2.5
2.5
–750
Min
D1
t
DISKEW
Max
Max
—
—
—
750
8
DISKEW
CISKEW
. This can be
Unit
) is the absolute
Unit
ns
ns
ns
ns
DDR2 SDRAM
Note
Note
2
3
3
3
15