mpc5200cvr400br2 Freescale Semiconductor, Inc, mpc5200cvr400br2 Datasheet - Page 26

• Manufacturer Part Number: mpc5200cvr400br2
• Description: Mpc5200b 32-bit Embedded Processor
• Manufacturer: Freescale Semiconductor, Inc

Electrical and Thermal Characteristics
3. REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ#
4. See the timing measurement conditions in the PCI Local Bus Specification [4].
For Measurement and Test Conditions, see the PCI Local Bus Specification [4].
3.3.7
The Local Plus Bus is the external bus interface of the MPC5200B. A maximum of eight configurable chip
selects (CS) are provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and
MUXED. The reference clock is the PCI CLK. The maximum bus frequency is 66 MHz.
Definition of Acronyms and Terms:
WS = Wait State
DC = Dead Cycle
LB = Long Burst
DS = Data Size in Bytes
tPCIck = PCI clock period
tIPBIck = IPBI clock period
3.3.7.1
26
have a setup of 5 ns at 66 MHz. All other signals are bused.
Sym
t
t
CSN
CSA
t
t
t
t
t
t
t
t
t
t
10
3
4
5
6
7
8
9
1
2
PCI CLK to CS assertion
PCI CLK to CS negation
CS pulse width
ADDR valid before CS assertion
ADDR hold after CS negation
OE assertion before CS assertion
OE negation before CS negation
RW valid before CS assertion
RW hold after CS negation
DATA output valid before CS assertion
DATA output hold after CS negation
DATA input setup before CS negation
Local Plus Bus
Non-MUXed Mode
Figure 10. Timing Diagram—IPBI and PCI clock (example ratio: 4:1)
PCI CLK
IPBI CLK
Description
Table 24. Non-MUXed Mode Timing
MPC5200B Data Sheet, Rev. 1
t
t
IPBIck
(2+WS)*t
PCIck
t
t
t
t
t
t
IPBIck
IPBIck
IPBIck
IPBIck
IPBIck
PCIck
Min
4.6
2.9
8.5
-
-
PCIck
(2+WS)*t
t
Max
10.6
PCIck
4.8
2.7
7.0
-
-
-
-
-
-
PCIck
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Freescale Semiconductor
Notes SpecID
(1)
(2)
A7.12
A7.10
A7.11
A7.1
A7.2
A7.3
A7.4
A7.5
A7.6
A7.7
A7.8
A7.9