mpc5200cvr400br2 Freescale Semiconductor, Inc, mpc5200cvr400br2 Datasheet - Page 34

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mpc5200cvr400br2

Manufacturer Part Number
mpc5200cvr400br2
Description
Mpc5200b 32-bit Embedded Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Electrical and Thermal Characteristics
34
t
Sym
t
t
t
t
2CYC
t
t
t
CYC
DVS
DVH
t
MLI
DH
DS
FS
LI
DMACK
DMARQ
(Drive)
(Host)
RDATA
(Drive)
WDATA
(Host)
DIOR
DIOW
(Host)
Min
114
235
The direction of signal assertion is towards the top of the page, and the
direction of negation is towards the bottom of the page, irrespective of the
electrical properties of the signal.
15
70
20
MODE 0
5
6
0
0
(ns)
Max
230
150
Min
156
10
75
48
20
MODE 1
5
6
0
0
t
I
(ns)
t
C
Table 29. Ultra DMA Timing Specification
Max
200
150
t
E
Figure 15. Multiword DMA Timing
t
t
Min
117
D
G
55
34
20
MPC5200B Data Sheet, Rev. 1
MODE 2
7
5
6
0
0
(ns)
Max
170 First STROBE time for drive to first negate DSTROBE
150 Limited Interlock time.
t
t
t
0
F
H
NOTE
Cycle time allowing for asymmetry and clock
variations from STROBE edge to STROBE edge
Two-cycle time allowing for clock variations, from
rising edge to next rising edge or from falling edge to
next falling edge of STROBE.
Data setup time at recipient.
Data hold time at recipient.
Data valid setup time at sender, to STROBE edge.
Data valid hold time at sender, from STROBE edge.
from STOP during a data-in burst.
Interlock time with minimum.
t
K
Comment
t
L
t
J
Freescale Semiconductor
SpecID
A8.26
A8.27
A8.28
A8.29
A8.30
A8.32
A8.33
A8.34
A8.31

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