mpc5200cvr400br2 Freescale Semiconductor, Inc, mpc5200cvr400br2 Datasheet - Page 48

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mpc5200cvr400br2

Manufacturer Part Number
mpc5200cvr400br2
Description
Mpc5200b 32-bit Embedded Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Electrical and Thermal Characteristics
3.3.12 MSCAN
The CAN functions are available as RX and TX pins at normal IO pads (I
is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured.
48
NOTES:
1
(CLKPOL=0)
(CLKPOL=1)
Inter Peripheral Clock is defined in the MPC5200B User Manual [1].
Sym
1
2
3
4
5
6
7
8
Output
MOSI
MISO
Input
Input
Input
SCK
Input
SCK
Cycle time
Clock high or low time
Slave select to clock delay
Output data valid
Input Data setup time
Input Data hold time
Slave disable lag time
Sequential Transfer delay
SS
Output timing is specified at a nominal 50 pF load.
Table 39. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1)
Figure 35. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)
4
3
Description
2
5
MPC5200B Data Sheet, Rev. 1
1
2
6
NOTE
15.0
50.0
15.0
Min
0.0
4
2
1
1024
Max
50.0
512
2
C1+GPTimer or PSC2). There
7
IP-Bus Cycle
IP-Bus Cycle
IP-Bus Cycle
Units
8
Freescale Semiconductor
ns
ns
ns
ns
ns
(1)
(1)
(1)
SpecID
A11.31
A11.32
A11.33
A11.34
A11.35
A11.36
A11.37
A11.38

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