gc80c590ae CORERIVER Semiconductor, gc80c590ae Datasheet - Page 96
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gc80c590ae
Manufacturer Part Number
gc80c590ae
Description
Flash / Isp / Iap 8-bit Turbo Microcontrollers
Manufacturer
CORERIVER Semiconductor
Datasheet
1.GC80C590AE.pdf
(132 pages)
- Current page: 96 of 132
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Appendix A : Instruction Set (1/19)
Note on Instruction Set and Addressing Modes
Notation
#data16
direct
addr16
addr11
#data
@Ri
rel
bit
Rn
Semiconductor Co., Ltd.
Register R0 ~ R7 of the currently selected Register Bank (RB0 ~ RB3).
The address of 8-bit internal data location.
This could be an IRAM location (0x00 ~ 0x7F; 128 bytes) or a SFR (0x80 ~ 0xFF).
8-bit IRAM location (0x00 ~ 0xFF; 256 bytes) addressed indirectly through register R0 or R1.
8-bit constant included in instruction.
16-bit constant included in instruction.
16-bit destination address.
Used by LCALL & LJMP. The branch can be anywhere within the 64kbytes program memory address
space. (MiDAS1.1 Family : 4kbytes program memory)
11-bit destination address.
Used by ACALL & AJMP. The branch will be within the same 2kbytes page of program memory as the
first byte of the following instruction.
Signed (2’s complement number) 8-bit offset byte.
Used by SJMP and all conditional jumps. Range is -128 to +127 byte relative to first byte of the
following instruction.
Direct addressed bit n IRAM of SFR.
Descriptions
MiDAS2.0 Family
[96]
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