gc80c590ae CORERIVER Semiconductor, gc80c590ae Datasheet - Page 122

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gc80c590ae

Manufacturer Part Number
gc80c590ae
Description
Flash / Isp / Iap 8-bit Turbo Microcontrollers
Manufacturer
CORERIVER Semiconductor
Datasheet
R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1)
R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
C0H.7
C0L.7
P3.7
SM0
C0L
C0H
P3
SCON1
Appendix B :
Quasi-bidirectional port with internal pull-up resistors.
When alternative function enabled, P3.X must be “1”.
SM0, SM1
SM2
(B0h) : Port 3 Register
(AEh) : Low Byte Register of PCA0 Counter
(AFh) : High Byte Register of PCA0 Counter
C0H.6
C0L.6
P3.6
SM1
(B1h) : Serial Port Control Register of UART1
: Enables the Automatic Address Recognition in Mode2 and
In Mode 1, the Validity of the Stop Bit is checked if SM2
In Mode0, SM2 should be “0”.
: Serial Port mode select.
C0L.5
C0H.5
P3.5
SM2
[0,0] : Mode0, 8-bit shift register (OSC/4)
[0,1] : Mode1, 8-bit UART (Variable)
[1,0] : Mode2, 9-bit UART (OSC/32 or OSC/16)
[1,1] : Mode3, 9-bit UART (Variable)
C0L.4
C0H.4
P3.4
REN
Semiconductor Co., Ltd.
C0L.3
C0H.3
P3.3
SFR Description [AEh ~ B4h]
TB8
C0H.2
C0L.2
P3.2
RB8
C0H.1
C0L.1
P3.1
TI
C0H.0
C0L.0
P3.0
RI
=1.
3.
R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1)
R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1)
R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1)
P5.7
P6.7
P7.7
P5
P6
P7
REN
TB8
RB8
TI
RI
Bidirectional port with direction and pull-up control.
Bidirectional port with direction and pull-up control.
Bidirectional port with direction and pull-up control.
(B2h) : Port 5 Register
(B3h) : Port 6 Register
(B4h) : Port 7 Register
P5.6
P6.6
P7.6
: Enable/Disable Reception.
: 9th data bit that will be transmitted in Mode2 and 3.
: 9th data bit that was received in Mode 2 and 3.
: Transmission interrupt flag. Must be cleared by S/W.
: Reception interrupt flag. Must be cleared by S/W.
In Mode1, RB8 is equal to stop bit if SM2 is “0”.
In Mode0, RB8 is not used.
P5.5
P6.5
P7.5
(8/17)
P5.4
P6.4
P7.4
MiDAS2.0 Family
P5.3
P6.3
P7.3
P5.2
P6.2
P7.2
P5.1
P6.1
P7.1
P5.0
P6.0
P7.0
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