gc80c590ae CORERIVER Semiconductor, gc80c590ae Datasheet - Page 118

no-image

gc80c590ae

Manufacturer Part Number
gc80c590ae
Description
Flash / Isp / Iap 8-bit Turbo Microcontrollers
Manufacturer
CORERIVER Semiconductor
Datasheet
C0CAP0L.7 C0CAP0L.6 C0CAP0L.5 C0CAP0L.4 C0CAP0L.3 C0CAP0L.2 C0CAP0L.1 C0CAP0L.0
C0CAP1L.7
C0CAP2L.7
C0CAP3L.7
C0CAP4L.7
C0CAP5L.7
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
C0CAP0L
C0CAP1L
C0CAP2L
C0CAP3L
C0CAP4L
C0CAP5L
Appendix B :
C0CAP1L.6
C0CAP2L.6
C0CAP3L.6
C0CAP4L.6
C0CAP5L.6
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
(92h) :
(93h) :
(94h) :
(95h) :
(96h) :
(97h) :
C0CAP1L.5
C0CAP2L.5
C0CAP3L.5
C0CAP4L.5
C0CAP5L.5
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
Low Capture/Compare Register of PCA0 MODULE0
Low Capture/Compare Register of PCA0 MODULE1
Low Capture/Compare Register of PCA0 MODULE2
Low Capture/Compare Register of PCA0 MODULE3
Low Capture/Compare Register of PCA0 MODULE4
Low Capture/Compare Register of PCA0 MODULE5
C0CAP1L.4
C0CAP2L.4
C0CAP3L.4
C0CAP4L.4
C0CAP5L.4
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
Semiconductor Co., Ltd.
SFR Description [92h ~ 99h]
C0CAP1L.3
C0CAP2L.3
C0CAP3L.3
C0CAP4L.3
C0CAP5L.3
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
C0CAP1L.2
C0CAP2L.2
C0CAP3L.2
C0CAP4L.2
C0CAP5L.2
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
C0CAP1L.1
C0CAP2L.1
C0CAP3L.1
C0CAP4L.1
C0CAP5L.1
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
C0CAP1L.0
C0CAP2L.0
C0CAP3L.0
C0CAP4L.0
C0CAP5L.0
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
SBUF.7
R/W(0)
SM0
SCON
SBUF
SM0, SM1
SM2
REN
TB8
RB8
TI
RI
The transmission buffer and the reception buffer are separated.
The transmission/reception buffers have the same address.
R/W(0)
SBUF.6
R/W(0)
(99h) : Serial Data Buffer Register of UART0
(98h) : Serial Port Control Register of UART0
SM1
: Enables the Automatic Address Recognition in Mode2 and 3.
: Enable/Disable Reception.
: 9th data bit that will be transmitted in Mode2 and 3.
: 9th data bit that was received in Mode 2 and 3.
: Transmission interrupt flag. Must be cleared by S/W.
: Reception interrupt flag. Must be cleared by S/W.
In Mode 1, the Validity of the Stop Bit is checked if SM2=1.
In Mode0, SM2 should be “0”.
In Mode1, RB8 is equal to stop bit if SM2 is “0”.
In Mode0, RB8 is not used.
R/W(0)
: Serial Port mode select.
R/W(0)
SBUF.5
SM2
[0,0] : Mode0, 8-bit shift register (OSC/4)
[0,1] : Mode1, 8-bit UART (Variable)
[1,0] : Mode2, 9-bit UART (OSC/32 or OSC/16)
[1,1] : Mode3, 9-bit UART (Variable)
(4/17)
R/W(0)
R/W(0)
SBUF.4
REN
MiDAS2.0 Family
R/W(0)
R/W(0)
SBUF.3
TB8
R/W(0)
R/W(0)
SBUF.2
RB8
R/W(0)
R/W(0)
SBUF.1
TI
R/W(0)
R/W(0)
SBUF.0
RI
[118]

Related parts for gc80c590ae