dp83840a National Semiconductor Corporation, dp83840a Datasheet - Page 58

• Manufacturer Part Number: dp83840a
• Description: 10/100 Mb/s Ethernet Physical Layer
• Manufacturer: National Semiconductor Corporation

Version A
5.0 DP83840A Application
5.1 Typical Board Level Application
Figure 20 shows a typical implementation of a 10/100
Mb/s Ethernet node application. This is given only to
indicate the major circuit elements of such a design. It is
not intended to be a full circuit diagram. For detailed
system level application information please contact your
National Semiconductor sales representative.
5.2 PLANE PARTITIONING
The recommendations for power plane partitioning
provided herein represent a more simplified approach
when compared to earlier recommendations. By
reducing the number of instances of plane partitioning
within a given system design, empirical data has shown
a
emissions testing. Additionally, be eliminating power
plane partitioning within the system Vcc and system
ground domains, specific impedance controlled signal
routing can remain uninterrupted.
Figure 21 illustrates one possible example of plane
partitioning and allocation assuming a typical four-layer
board design. The minimum gap between any two
planes on a single layer must be held to 125 mils.
resultant
CONTROLLER
ACCESS
MEDIA
improvement
RXD<3:0>
TXD<3:0>
RX_CLK
TX_CLK
FIGURE 20. Typical 10/100 Ethernet Node Design Device Interconnection
RX_DV
RX_ER
TX_EN
MDIO
MDC
CRS
COL
(reduction)
4.7k
V
CC
75, 76, 77, 78
X1
55, 56, 57, 58
82
74
66
65
62
64
63
72
67
33
DP83840A
GND
V
4
CC
in
GND
26, 25
24, 23
21, 20
17, 16
radiated
5, 6
8, 7
2
54
53
49
50 MHz
0.005%
OSCIN
V
CC
58
SPEED_10
ENCSEL
By placing chassis ground on the top and bottom layers,
additional EMI shielding is created around the 125 Mb/s
signal traces that must be routed between the magnetics and
the RJ45-8 media connector. The example in Figure 17
assumes
techniques for trace routing.
5.3 POWER AND GROUND FILTERING
Sufficient filtering between the DP83840A power and ground
pins placed as near to these pins as possible is
recommended. Figure 22 suggests one option for device
noise filtering including special consideration for the sensitive
analog and PLL power pins. The actual connection from
ANAVCC to the 4
etch’ (20 to 30 mils wide) of minimum length. The same
technique should be implemented for the connection from
PLLVCC to its 10 resistor.
The example provided in Figure 22 has been designed to
minimize the number of physical decoupling components
while still maintaining good overall device decoupling.
TD +/-
RD +/-
SD +/-
LBEN
12
15, 16
25, 24
20, 21
19
the
TXU+/-
TXS+/-
RXI+/-
TWISTER
DP83223
GND
V
CC
use
9, 8
2, 1
resistor should be implemented as a ‘fat
of
National Semiconductor
RXD +/-
TXD +/-
Micro-Strip
impedance
1
2
3
6
control
RD+
RJ-45
TD+
TD-
RD-