dp83840a National Semiconductor Corporation, dp83840a Datasheet - Page 8

• Manufacturer Part Number: dp83840a
• Description: 10/100 Mb/s Ethernet Physical Layer
• Manufacturer: National Semiconductor Corporation

Version A
2.0 Pin Description
2.4 CLOCK INTERFACE
REFIN
CLK25M
OSCIN
X2
X1
Signal Name
I = TTL/CMOS input
Type
O, Z
O
I
I
I
O = TTL/CMOS output
(Continued)
Pin #
86
81
34
33
2
REFERENCE INPUT: 25 MHz TTL reference clock input. This clock can be
supplied from an external oscillator module or from the CLK25M output (pin 81).
25 MHz CLOCK OUTPUT: Derived from the 50 MHz OSCIN input. When not in
use, this clock output may be shut off through software by setting bit 7 of the PCS
Configuration Register at address 17h. This output remains unaffected by
hardware and software reset.
OSCILLATOR INPUT: 50 MHz 50 ppm e xternal TTL oscillator input. If not used,
pull down to GND (4.7 k pull down resistor suggested).
CRYSTAL OSCILLATOR OUTPUT: External 20 MHz
connection. Used for 10BASE-T timing. When using an external 20 MHz oscillator
connected to X1 or with no reference to X1, leave this pin unconnected.
CRYSTAL OSCILLATOR INPUT: External 20 MHz 0.005% crystal connection.
Used for 10BASE-T timing and Auto-Negotiation. If not used, this pin should be
pulled up to V
DP83840A detects this condition, enables the internal 2.5 divider , and switches
the 10 Mb/s and Auto-Negotiation circuitry to the internally derived 20 MHz clock.
Z = TRI-STATE output
CC.
8
(4.7 k
pull up resistor suggested). When pulled high, the
J = IEEE 1149.1 pin
Description
National Semiconductor
0.005% crystal