dp83840a National Semiconductor Corporation, dp83840a Datasheet - Page 87

• Manufacturer Part Number: dp83840a
• Description: 10/100 Mb/s Ethernet Physical Layer
• Manufacturer: National Semiconductor Corporation

Version A
8.0 Electrical Specifications
8.10 Loopback Timing
8.10.1 10 Mb/s and 100 Mb/s Loopback Timing
Note 1: The 100BASE-X PMD Loopback option timing is dependent on the external transceiver loopback timing and is therefore not defined herein.
Note 2: The TD+/- outputs of the DP83840A can be enabled or disabled during loopback operation via the LBK_XMT_DS bit (bit 5 of the LBREMR register).
Note 3: Due to the nature of the descrambler function, all 100BASE-X Loopback modes, with the exception of Remote Loopback, will cause an initial “dead-
time” of up to 750 s during which time no data will be present at the receive MII outputs. The 100BASE-X timing shown here in section 6.3.16 is based on
device delays after the initial 750 s “dead-time”
Note 4: During 10BASE-T loopback (serial or nibble mode) both the TXU+/- and TXS+/- outputs remain inactive.
Parameter
T1
TX_EN to RX_DV Loopback
RXD[3:0]
TXD[3:0]
TX_CLK
RX_CLK
TX_EN
RX_DV
CRS
Description
(Continued)
100 Mb/s (note 1), (note2), (note3)
10 Mb/s serial mode (note 4)
10 Mb/s nibble mode (internal loopback)
10 Mb/s nibble mode (normal operation)
T1
87
Notes
Min
Typ
Max
240
250
2
2
Units
ns
ns
s
s