dp83840a National Semiconductor Corporation, dp83840a Datasheet - Page 86

• Manufacturer Part Number: dp83840a
• Description: 10/100 Mb/s Ethernet Physical Layer
• Manufacturer: National Semiconductor Corporation

Version A
8.0 Electrical Specifications
8.9 Reset Timing
8.9.1 Hardware Reset Timing
Note: Software Reset should be initiated no sooner then 500 s after power-up or the deassertion of hardware reset
Note: The timing for Hardware Reset Option 2 is equal to parameter T1 plus parameter T2 (501 s total).
Parameter
T1
T2
T3
T4
T5
Dual Function Pins
Become Enabled As Outputs
Reset (option #1)
Reset (option #2)
Latch-In of Hardware
Configuration Pins
Hardware
Hardware
Internal Reset Time
Hardware RESET Pulse Width
Post Reset Stabilization time
prior to MDC preamble for
register accesses
Hardware Configuration Latch-
in Time from the Deassertion of
Reset (either soft or hard)
Hardware Configuration pins
transition to output drivers
MDC
Vcc
Description
(Continued)
T1
MDIO is pulled high for 32 bit serial
management initialization
Hardware Configuration Pins are
described in section 3.10
It is important to choose pull-up and/or
pull-down resistors for each of the
hardware configuration pins that provide
fast RC time constants in order to latch-in
the proper value prior to the pin
transitioning to an output driver
T2
86
Notes
T4
T3
T5
input
32 clocks
.
Min
500
500
1
output
Typ
800
800
Max
Units
ns
ns
s
s
s