adav400kstz-reel Analog Devices, Inc., adav400kstz-reel Datasheet - Page 15

• Manufacturer Part Number: adav400kstz-reel
• Description: Audio Codec With Embedded Sigmadsp Processor
• Manufacturer: Analog Devices, Inc.

CONTROL PORT
The ADAV400 control port has full read and write capability to
all registers and RAMs with the exception of the data RAM,
which is only accessible by the DSP core. Single or burst mode
reads and writes are supported. A typical word consists of the
chip address, the register or RAM subaddress, and the data to
be written. The number of bytes per data-word depends on the
address of the location being written to or read from.
The first byte of a control word (Byte 0) contains the 7-bit chip
address plus the R/ W bit. The next two bytes (Byte 1 and Byte 2)
together form the subaddress of the memory or register location
within the ADAV400. All subsequent bytes contain data that
can be writes to the control register or updates to the program
and parameter memories. Table 16 to Table 25 provide more
details on the I
The ADAV400 has several mechanisms for updating signal
processing parameters in real time without causing pops or
clicks. In cases where large blocks of data need to be transferred,
it is recommended to mute the output of the DSP core by setting
Bit 9 of the audio core control register to 0, and then load the
new data and set Bit 9 back to 1. This is typically done during
the booting sequence at startup or when loading a new program
into RAM.
In cases where only a few parameters need to be changed—for
example, updating a biquad—the new parameters can be loaded
without halting the program. To avoid unwanted pops or clicks
in the output during the loading sequence, the DSP core uses an
internal safe load mechanism that buffers the data and only
updates the parameter memory at the end of the sample period
and before the start of the next sample period.
I
The ADAV400 supports a 2-wire serial (I
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the ADAV400 and the system I
The ADAV400 is always a slave on the I
that it never initiates a data transfer. Each slave device is
recognized by a unique address.
The ADAV400 has four possible slave addresses, two for writing
operations and two for reading operations. These are unique
addresses for the device and are illustrated in Table 5. The LSB
of the byte sets either a read or a write operation; Logic Level 1
corresponds to a read operation, and Logic Level 0 corresponds
to a write operation. The seventh bit of the address is set by tying
the AD0 pin of the ADAV400 to Logic Level 0 or Logic Level 1.
2
C PORT
2
C write and read formats.
2
2
C bus, which means
C master controller.
2
C-compatible)
Rev. A | Page 15 of 36
Table 5. I
AD0
0
0
1
1
Addressing
Initially, all devices on the I
the devices monitor the SDA and SCL lines for a start condition
and the proper address. The I
by establishing a start condition, defined by a high-to-low
transition on SDA while SCL remains high. This indicates that
an address/data stream follows. All devices on the bus respond
to the start condition and read the next byte (7-bit address +
R/ W bit) MSB first. The device that recognizes the transmitted
address responds by pulling the data line low during the ninth
clock pulse. This ninth bit is known as an acknowledge bit. All
other devices on the bus revert to an idle condition. The R/ W
bit determines the direction of the data. A Logic Level 0 on the
LSB of the first byte means the master writes information to the
peripheral. A Logic Level 1 on the LSB of the first byte means
the master reads information from the peripheral. A data
transfer takes place until a stop condition is encountered. A stop
condition occurs when SDA transitions from low to high while
SCL is held high. Figure 20 shows the timing of an I
Burst mode addressing, where the subaddresses are automatically
incremented at word boundaries, can be used for writing large
amounts of data to contiguous memory locations. This
increment happens automatically if a stop condition is not
encountered after a single word write. A data transfer is always
terminated by a stop condition.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, it causes an
immediate jump to the idle condition. During a given SCL high
period, the user should only issue one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADAV400 does not issue an acknowledge and reverts to an idle
state. If the user exceeds the highest subaddress while in auto-
increment mode, one of two actions is taken. In read mode, the
ADAV400 outputs the highest subaddress register contents until
the master device issues a no acknowledge, indicating the end of
a read. A no acknowledge condition is where the SDA line is not
pulled low on the ninth clock pulse on SCL. If the highest
subaddress location is reached while in write mode, the data for
the invalid byte is not loaded into any subaddress register, a no
acknowledge is issued by the ADAV400, and the part returns to
the idle condition.
2
C Addresses
R/W
0
1
0
1
2
C bus are in an idle state, wherein
2
C master initiates a data transfer
Slave Address
0x28
0x29
0x2A
0x2B
ADAV400
2
C write.