adav400kstz-reel Analog Devices, Inc., adav400kstz-reel Datasheet - Page 23

• Manufacturer Part Number: adav400kstz-reel
• Description: Audio Codec With Embedded Sigmadsp Processor
• Manufacturer: Analog Devices, Inc.

SAFE LOAD REGISTERS
Many applications require real-time control of signal processing
parameters, such as filter coefficients, mixer gains, multichannel
virtualizing parameters, or dynamics processing curves.
For example, if we consider a biquad to prevent instability from
occurring, all five parameters of a biquad filter must be updated
at the same time. Otherwise, the filter may execute with a mix
of old and new coefficients for one or two audio frames. To
eliminate this problem, the ADAV400 uses the safe load registers;
there are five registers for the 28-bit parameter data and five for
the parameter addresses. These addresses will indirectly address
either the parameter RAM or the target/slew RAM.
Once these registers are loaded, the appropriate initiate safe
transfer bit (there are separate bits for parameter and target/slew
loads) in the audio core control register should be set.
The last five instructions of the program RAM are used for the
safe load process, so the program length should be limited to
2555 cycles (2560 − 5). It is guaranteed that the safe load occurs
within one LRCLK period (21 μs at f
safe transfer bit being set. Safe load only updates those safe load
registers that have been loaded with new data since the last safe
load operation. For example, if only two parameters or target
RAM locations are to be updated, it is only necessary to load
two of the safe load registers; the other safe load registers are
ignored because they contain old data.
DATA CAPTURE REGISTERS
Data capture registers are used for debugging user-programmed
blocks and are not required when using pre-existing library blocks.
Figure 30. Slew RAM—Constant Time Update Decreasing Ramp, Full Scale
–0.2
–0.4
–0.6
–0.8
–1.0
1.0
0.8
0.6
0.4
0.2
0
0
5
10
15
TIME (ms)
S
20
= 48 kHz) of the initiate
25
30
35
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The ADAV400 data capture feature allows the data at any node
in the signal processing flow to be sent to one of six registers
that can be read by the control port or to a serial output pin.
Use this feature to monitor and display information about
internal signal levels or compressor/limiter activity.
The ADAV400 contains six independent data capture registers
that can be read via the I
monitoring static signals. In addition, two I
capture registers are available for monitoring dynamic signals.
For each of the data capture registers, a capture count and a
register select must be set. The capture count is a number
between 0 and 2559 that corresponds to the program step
number where the capture will occur (see Table 15).
Table 15. Data Capture Control Registers
Register Bits
13:2
1:0
The register select field selects which one of four registers
within the DSP core will be transferred to the data capture
register when the program counter equals the capture count.
The capture count and register select bits are set by writing to
one of the eight data capture registers at the following register
addresses:
•
•
•
•
•
•
•
•
The captured data is in 5.19 twos complement data format for
all eight register select fields. The four LSBs are truncated from
the internal 5.23 data-word.
The formats for writing and reading to the data capture
registers are listed in Table 22 and Table 23.
4170: Control Port Data Capture Setup Register 0
4171: Control Port Data Capture Setup Register 1
4172: Control Port Data Capture Setup Register 2
4173: Control Port Data Capture Setup Register 3
4174: Control Port Data Capture Setup Register 4
4175: Control Port Data Capture Setup Register 5
4176: Digital Out Data Capture Setup Register 0
4177: Digital Out Data Capture Setup Register 1
Function
12-bit program counter address
Register select
00 = Mult_X_input
01 = Mult_Y_input
10 = MAC_output
11 = Accum_fback
2
C control port and can be used for
2
S digital output
ADAV400