adav400kstz-reel Analog Devices, Inc., adav400kstz-reel Datasheet - Page 19

• Manufacturer Part Number: adav400kstz-reel
• Description: Audio Codec With Embedded Sigmadsp Processor
• Manufacturer: Analog Devices, Inc.

RAMS AND REGISTERS
Table 10. Control Port Addresses
I
0 to 1023 (0x0000 to 0x03FF)
1024 to 3584 (0x0400 to 0x0E00)
4096 to 4159 (0x1000 to 0x103F)
4160 to 4164 (0x1040 to 0x1044)
4165 to 4169 (0x1045 to 0x1049)
4170 to 4175 (0x104A to 0x104F)
4176 to 4177 (0x1050 to 0x1051)
4178 (0x1052)
4179 (0x1053)
4180 (0x1054)
4181 (0x1055)
4182 (0x1056)
4183 (0x1057)
4184 (0x1058)
4185 (0x1059)
4186 (0x105A)
4365 (0x110D)
Table 11. RAM Read/Write Modes
Memory
Parameter RAM
Program RAM
Target/Slew RAM
1
CONTROL PORT ADDRESSING
Table 10 shows the addressing of the RAM and register spaces
on the ADAV400. The address space encompasses a set of
registers and three RAMs: parameter, program, and target/slew.
Table 11 lists the sizes and available writing modes of the
parameter, program, and target/slew RAMs.
PARAMETER RAM CONTENTS
The parameter RAM is 28 bits wide and occupies Address 0 to
Address 1023. The parameter RAM is initialized to all 0s on
power-up. The data format of the parameter RAM is twos
complement 5.23. This means that the coefficients can range
from +16.0 (−1 LSB) to −16.0, with 1.0 represented by the
binary word 0000 1000 0000 0000 0000 0000 0000.
2
To avoid clicks or pops, mute the DSP core first.
C Subaddress
Size
1024 × 28
2560 × 42
64 × 34
Subaddress Range
0 to 1023
(0x0000 to 0x03FF)
1024 to 3584
(0x0400 to 0x0E00)
4096 to 4159
(0x1000 to 0x1044)
Program RAM
Audio core control register
RAM modulo control register
Serial output control register
Serial input control register
SRC serial port control register
ADC input mux control register
Power control register
User Control 1 register
User Control 2 register
DAC amplifier register
Register Name
Parameter RAM
Target/slew RAM
Parameter RAM Data Safe Load Register [0:4]
Parameter RAM Indirect Address Safe Load Register [0:4]
Data Capture Register [0:5] (control port readback)
Data capture registers (digital output)
Rev. A | Page 19 of 36
Read
Yes
Yes
No
Write
Yes
Yes
Yes
Options for Parameter Updates
The parameter RAM can be written to and read from using one
of the two following methods:
•
•
Direct Read/Write.
This method allows direct access to the program and
parameter RAMs. It is normally used during a complete
new load of the RAMs using burst mode addressing. To
avoid clicks or pops in the outputs, it is recommended to set
the clear registers bit in the audio core control register to 0.
Safe Load Write.
Up to five safe load registers can be loaded with parameter
RAM address data. The data is transferred to the requested
address when the RAM is idle. It is recommended to use
this method for dynamic updates during run time. For
example, a complete update of one biquad section can
occur in one audio frame. This method is not available for
writing to the program RAM or control registers. The
following sections discuss these two options in more detail.
Burst Mode Available
No
Yes
Yes
Read/Write Word Length
Write: 4 bytes; read: 4 bytes
Write: 6 bytes; read: 6 bytes
Write: 5 bytes; read: N/A
Write: 2 bytes; read: N/A
Write: 2 bytes; read: 3 bytes
Write: 2 bytes; read: N/A
Write: 2 bytes; read: 2 bytes
Write: 1 byte; read: 1 byte
Write: 2 bytes; read: 2 bytes
Write: 1 byte; read: 1 byte
Write: 1 byte; read: 1 byte
Write: 2 bytes; read: 2 bytes
Write: 2 bytes; read: 2 bytes
Write: 2 bytes; read: 2 bytes
Write: 2 bytes; read: 2 bytes
Write: 2 bytes; read: 2 bytes
Write: 5 bytes; read: N/A
Write Modes
Direct write,
Direct write
Safe load write
1
1
safe load write
ADAV400