at83c5122 ATMEL Corporation, at83c5122 Datasheet - Page 115

• Manufacturer Part Number: at83c5122
• Description: At83c5123 C51 Microcontroller With Usb And Smart Card Reader Interfaces
• Manufacturer: ATMEL Corporation

USB Interrupt System
Interrupt System Priorities
Figure 63. USB Interrupt Control System
Interrupt Control System
4202E–SCR–06/06
D+
D-
Controller
USB
Table 63. Priority Levels
As shown in Figure 64, many events can produce a USB interrupt:
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•
•
•
•
•
•
•
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TXCMPL: Transmitted In Data (Table 70 on page 121). This bit is set by hardware
when the Host accept a In packet.
RXOUTB0: Received Out Data Bank 0 (Table 70 on page 121). This bit is set by
hardware when an Out packet is accepted by the endpoint and stored in bank 0.
RXOUTB1: Received Out Data Bank 1 (only for Ping-Pong endpoints) (Table 70 on
page 121). This bit is set by hardware when an Out packet is accepted by the
endpoint and stored in bank 1.
RXSETUP: Received Setup (Table 70 on page 121). This bit is set by hardware
when an SETUP packet is accepted by the endpoint.
NAKIN and NAKOUT: These bits are set by hardware when a Nak Handshake has
been received on the corresponding endpoint. These bits are cleared by software.
STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table on page
122). This bit is set by hardware when a STALL handshake has been sent as
requested by STALLRQ, and is reset by hardware when a SETUP packet is
received.
SOFINT: Start Of Frame Interrupt (Table 65 on page 118). This bit is set by
hardware when a USB start of frame packet has been received.
WUPCPU: Wake-Up CPU Interrupt (Table 65 on page 118). This bit is set by
hardware when a USB resume is detected on the USB bus, after a SUSPEND state.
SPINT: Suspend Interrupt (Table 65 on page 118). This bit is set by hardware when
a USB suspend is detected on the USB bus.
IPHUSB
0
0
1
1
EUSB
IEN1.6
Interrupt Enable
IEN0.7
EA
IPLUSB
0
1
0
1
Priority Enable
IPH/L
00
01
10
11
Lowest Priority Interrupts
USB Priority Level
AT8xC5122/23
3 Highest
0 Lowest
1
2
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