at83c5122 ATMEL Corporation, at83c5122 Datasheet - Page 124

• Manufacturer Part Number: at83c5122
• Description: At83c5123 C51 Microcontroller With Usb And Smart Card Reader Interfaces
• Manufacturer: ATMEL Corporation

124
AT8xC5122/23
Table 74. USB Endpoint Interrupt Register - UEPINT (S:F8h read-only)
Reset Value = 0000 0000b
Number
Bit
7
6
5
4
3
2
1
0
7
-
Mnemonic Description
EP6INT
EP5INT
EP4INT
EP3INT
EP2INT
EP1INT
EP0INT
Bit
EP6INT
-
6
Reserved
The value read from these bits is always 0. Do not change this bit.
Endpoint 6 Interrupt
This bit is set by hardware when an interrupt has been detected on the endpoint 6.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP6INTE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the interrupt sources are cleared.
Endpoint 5 Interrupt
This bit is set by hardware when an interrupt has been detected on the endpoint 5.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP5INTE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the interrupt sources are cleared.
Endpoint 4 Interrupt
This bit is set by hardware when an interrupt has been detected on the endpoint 4.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP4INTE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the interrupt sources are cleared.
Endpoint 3 Interrupt
This bit is set by hardware when an interrupt has been detected on the endpoint 3.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP3INTE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the interrupt sources are cleared.
Endpoint 2 Interrupt
This bit is set by hardware when an interrupt has been detected on the endpoint 2.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP2INTE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the interrupt sources are cleared.
Endpoint 1 Interrupt
This bit is set by hardware when an interrupt has been detected on the endpoint 1.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP1INTE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the interrupt sources are cleared.
Endpoint 0 Interrupt
This bit is set by hardware when an interrupt has been detected on the endpoint 0.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP0INTE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the interrupt sources are cleared.
EP5INT
5
EP4INT
4
EP3INT
3
EP2INT
2
EP1INT
1
4202E–SCR–06/06
EP0INT
0