isp1562 NXP Semiconductors, isp1562 Datasheet - Page 28

• Manufacturer Part Number: isp1562
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 37.
Table 38.
Address: Value read from address 34h + 6h
Table 39.
Address: Value read from address 34h + 6h
ISP1562_2
Product data sheet
Bit
1 to 0
Bit
Symbol
Reset
Access
Bit
7
6
5 to 0
Address: Value read from address 34h + 4h
Symbol
PS[1:0]
Symbol
BPCC_EN
B2_B3#
reserved
PMCSR - Power Management Control/Status register bit description
PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit allocation
PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit description
8.2.3.5 PMCSR_BSE register
BPCC_EN
R
7
0
Description
Power State: This two-bit field is used to determine the current power state of the EHCI function and
to set the function into a new power state. The definition of the field values is given as:
00b — D0
01b — D1
10b — D2
11b — D3
If the software attempts to write an unsupported, optional state to this field, the write operation must
complete normally on the bus; however, data is discarded and no status change occurs.
The PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI
bridge-specific functionality and is required for all PCI-to-PCI bridges. The bit allocation of
this register is given in
Table 40.
Originating device’s
bridge PM state
D0
D1
Description
Bus Power/Clock Control Enable:
1 — Indicates that the bus power or clock control mechanism as defined in
0 — Indicates that the bus or power control policies as defined in
When the bus power or clock control mechanism is disabled, the bridge’s PMCSR Power State
(PS) field cannot be used by the system software to control the power or clock of the bridge’s
secondary bus.
B2/B3 support for D3
result of programming the function to D3
1 — Indicates that when the bridge function is programmed to D3
clock will be stopped (B2).
0 — Indicates that when the bridge function is programmed to D3
its power removed (B3).
This bit is only meaningful if bit 7 (BPCC_EN) is logic 1.
-
B2_B3#
hot
R
6
0
PCI bus power and clock control
R
5
0
Secondary bus
PM state
B0
B1
hot
Table
Rev. 02 — 1 March 2007
: The state of this bit determines the action that is to occur as a direct
38.
R
4
0
hot
Resultant actions by bridge (either direct or
indirect)
none
none
.
R
3
0
reserved
…continued
R
2
0
HS USB PCI Host Controller
hot
hot
Table 40
, its secondary bus will have
, its secondary bus’s PCI
are disabled.
Table 40
R
1
0
© NXP B.V. 2007. All rights reserved.
ISP1562
is enabled.
R
0
0
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