isp1562 NXP Semiconductors, isp1562 Datasheet - Page 45

• Manufacturer Part Number: isp1562
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 63.
Address: Content of the base address register + 28h
[1]
Table 64.
Address: Content of the base address register + 28h
Table 65.
Address: Content of the base address register + 2Ch
ISP1562_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 4
3 to 0
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Symbol
BHED[27:0] Bulk Head ED: The Host Controller traverses the bulk list starting with the HcBulkHeadED pointer.
reserved
HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit allocation
HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit description
HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit allocation
11.1.11 HcBulkHeadED register
11.1.12 HcBulkCurrentED register
R/W
R/W
R/W
R/W
R/W
31
23
15
31
0
0
0
7
0
0
Description
The content is loaded from HCCA during the initialization of the Host Controller.
-
This register (see
This register contains the physical address of the current endpoint of the bulk list. The
endpoints are ordered according to their insertion to the list because the bulk list must be
served in a round-robin fashion.
The bit allocation is given in
R/W
R/W
R/W
R/W
R/W
30
22
14
30
0
0
0
6
0
0
BHED[3:0]
Table
R/W
R/W
R/W
R/W
R/W
29
21
13
29
0
0
0
5
0
0
Rev. 02 — 1 March 2007
63) contains the physical address of the first ED of the bulk list.
Table
R/W
R/W
R/W
R/W
R/W
28
20
12
28
0
0
0
4
0
0
BHED[27:20]
BHED[19:12]
BCED[27:20]
BHED[11:4]
65.
R/W
R/W
R/W
R/W
R/W
27
19
11
27
0
0
0
3
0
0
R/W
R/W
R/W
R/W
R/W
26
18
10
26
0
0
0
2
0
0
HS USB PCI Host Controller
reserved
[1]
R/W
R/W
R/W
R/W
R/W
25
17
25
0
0
9
0
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1562
R/W
R/W
R/W
R/W
R/W
24
16
24
0
0
8
0
0
0
0
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