isp1582 NXP Semiconductors, isp1582 Datasheet - Page 38

• Manufacturer Part Number: isp1582
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 43.
Table 45.
ISP1582_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Code
00h
01h
02h to 0Dh -
0Eh
DMA Command register: bit allocation
DMA commands
Name
GDMA Read
GDMA Write
Validate Buffer Validate Buffer (for debugging only): Request from the microcontroller to validate the
8.4.1 DMA Command register (address: 30h)
W
7
1
1
There are three interrupts programmable to differentiate the method of DMA termination:
bits INT_EOT, EXT_EOT and DMA_XFER_OK in the DMA Interrupt Reason register. For
details, see
Table 42.
Remark: The DMA bus defaults to 3-state, until a DMA command is executed. All the
other control signals are not 3-stated.
The DMA Command register is a 1-byte register (for bit allocation, see
initiates all DMA transfer activity on the DMA controller. The register is write-only: reading
it will return FFh.
Remark: The DMA bus will be in 3-state, until a DMA command is executed.
Table 44.
Control bits
DMA Configuration register
MODE[1:0]
WIDTH
DIS_XFER_CNT
DMA Hardware register
EOT_POL
ENDIAN[1:0]
ACK_POL, DREQ_POL,
WRITE_POL, READ_POL
Bit
7 to 0
•
Issuing a GDMA stop command
Description
Generic DMA IN token transfer: Data is transferred from the external DMA bus to the
internal buffer. Strobe: DIOW by external DMA controller.
Generic DMA OUT token transfer: Data is transferred from the internal buffer to the external
DMA bus. Strobe: DIOR by external DMA controller.
reserved
endpoint buffer, following a DMA-to-USB data transfer.
W
6
1
1
Control bits for GDMA read/write (opcode = 00h/01h)
DMA Command register: bit description
Table
Symbol
DMA_CMD[7:0]
54.
Rev. 06 — 20 September 2007
W
5
1
1
Description
determines the active read/write data strobe signals
selects the DMA bus width: 8 or 16 bits
disables the use of the DMA Transfer Counter
selects the polarity of the EOT signal
determines whether the data is to be byte swapped or
normal; applicable only in 16-bit mode
select polarity of DMA handshake signals
Description
DMA command code; see
DMA_CMD[7:0]
W
4
1
1
W
3
1
1
Hi-Speed USB Peripheral Controller
Table
W
2
1
1
45.
W
1
1
1
Table
© NXP B.V. 2007. All rights reserved.
ISP1582
Reference
Table 48
Table 50
43) that
W
0
1
1
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