isp1582 NXP Semiconductors, isp1582 Datasheet - Page 66

• Manufacturer Part Number: isp1582
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
22. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Operation truth table for SoftConnect . . . . . . .20
Table 11. Operation truth table for clock off during
Table 12. Operation truth table for back voltage
Table 13. Operation truth table for OTG . . . . . . . . . . . . .21
Table 14. Register overview . . . . . . . . . . . . . . . . . . . . . .22
Table 15. Address register: bit allocation . . . . . . . . . . . .24
Table 16. Address register: bit description . . . . . . . . . . .24
Table 17. Mode register: bit allocation . . . . . . . . . . . . . . .24
Table 18. Mode register: bit description . . . . . . . . . . . . .24
Table 19. Status of the chip . . . . . . . . . . . . . . . . . . . . . . .25
Table 20. Interrupt Configuration register: bit allocation .26
Table 21. Interrupt Configuration register: bit description 26
Table 22. Debug mode settings . . . . . . . . . . . . . . . . . . . .26
Table 23. OTG register: bit allocation . . . . . . . . . . . . . . .26
Table 24. OTG register: bit description . . . . . . . . . . . . . .27
Table 25. Interrupt Enable register: bit allocation . . . . . .29
Table 26. Interrupt Enable register: bit description . . . . .29
Table 27. Endpoint Index register: bit allocation . . . . . . .30
Table 28. Endpoint Index register: bit description . . . . . .31
Table 29. Addressing of endpoint buffers . . . . . . . . . . . .31
Table 30. Control Function register: bit allocation . . . . . .31
Table 31. Control Function register: bit description . . . . .32
Table 32. Data Port register: bit allocation . . . . . . . . . . .33
Table 33. Data Port register: bit description . . . . . . . . . .33
Table 34. Buffer Length register: bit allocation . . . . . . . .34
Table 35. Buffer Length register: bit description . . . . . . .34
Table 36. Buffer Status register: bit allocation . . . . . . . . .35
Table 37. Buffer Status register: bit description . . . . . . . .35
Table 38. Endpoint MaxPacketSize register: bit
Table 39. Endpoint MaxPacketSize register: bit
Table 40. Endpoint Type register: bit allocation . . . . . . . .36
Table 41. Endpoint Type register: bit description . . . . . . .37
Table 42. Control bits for GDMA read/write (opcode =
ISP1582_6
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
ISP1582 pin status . . . . . . . . . . . . . . . . . . . . . .11
ISP1582 output status . . . . . . . . . . . . . . . . . . .12
Power modes . . . . . . . . . . . . . . . . . . . . . . . . . .18
Operation truth table for SoftConnect . . . . . . .19
Operation truth table for clock off during
suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Operation truth table for back voltage
compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Operation truth table for OTG . . . . . . . . . . . . .20
suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Rev. 06 — 20 September 2007
Table 43. DMA Command register: bit allocation . . . . . . 38
Table 44. DMA Command register: bit description . . . . . 38
Table 45. DMA commands . . . . . . . . . . . . . . . . . . . . . . . 38
Table 46. DMA Transfer Counter register: bit allocation . 39
Table 47. DMA Transfer Counter register: bit description 40
Table 48. DMA Configuration register: bit allocation . . . . 40
Table 49. DMA Configuration register: bit description . . . 40
Table 50. DMA Hardware register: bit allocation . . . . . . . 41
Table 51. DMA Hardware register: bit description . . . . . 41
Table 52. DMA Interrupt Reason register: bit allocation . 42
Table 53. DMA Interrupt Reason register: bit description 42
Table 54. Internal EOT-functional relation with bit
Table 55. DMA Interrupt Enable register: bit allocation . . 43
Table 56. DMA Endpoint register: bit allocation . . . . . . . 44
Table 57. DMA Endpoint register: bit description . . . . . . 44
Table 58. DMA Burst Counter register: bit allocation . . . 44
Table 59. DMA Burst Counter register: bit description . . 44
Table 60. Interrupt register: bit allocation . . . . . . . . . . . . 45
Table 61. Interrupt register: bit description . . . . . . . . . . . 45
Table 62. Chip ID register: bit allocation . . . . . . . . . . . . . 47
Table 63. Chip ID register: bit description . . . . . . . . . . . . 47
Table 64. Frame Number register: bit allocation . . . . . . . 47
Table 65. Frame Number register: bit description . . . . . . 48
Table 66. Scratch register: bit allocation . . . . . . . . . . . . . 48
Table 67. Scratch register: bit description . . . . . . . . . . . . 48
Table 68. Unlock Device register: bit allocation . . . . . . . 48
Table 69. Unlock Device register: bit description . . . . . . 49
Table 70. Test Mode register: bit allocation . . . . . . . . . . . 49
Table 71. Test Mode register: bit description . . . . . . . . . 49
Table 72. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 73. Recommended operating conditions . . . . . . . . 50
Table 74. Static characteristics: supply pins . . . . . . . . . . 50
Table 75. Static characteristics: digital pins . . . . . . . . . . 51
Table 76. Static characteristics: OTG detection . . . . . . . 51
Table 77. Static characteristics: analog I/O pins DP and
Table 78. Dynamic characteristics . . . . . . . . . . . . . . . . . 52
Table 79. Dynamic characteristics: analog I/O pins DP and
Table 80. Register access timing parameters: separate
Table 81. GDMA mode timing parameters . . . . . . . . . . . 55
Table 82. SnPb eutectic process (from J-STD-020C) . . . 61
Table 83. Lead-free process (from J-STD-020C) . . . . . . 61
Table 84. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 85. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 64
00h/01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DMA_XFER_OK . . . . . . . . . . . . . . . . . . . . . . . 43
DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
address and data buses . . . . . . . . . . . . . . . . . 54
Hi-Speed USB Peripheral Controller
© NXP B.V. 2007. All rights reserved.
ISP1582
continued >>
66 of 69