cp2200 Silicon Laboratories, cp2200 Datasheet - Page 23

• Manufacturer Part Number: cp2200
• Description: Single-chip Ethernet Controller
• Manufacturer: Silicon Laboratories

7. Internal Memory and Registers
The CP2200/1 is controlled through direct and indirect registers accessible through the parallel host interface. The
host interface provides an 8-bit address space, of which there are 114 valid direct register locations (see Table 11
on page 25). All remaining addresses in the memory space are reserved and should not be read or written. The
direct registers provide access to the RAM buffers, Flash memory, indirect MAC configuration registers, and other
status and control registers for various device functions.
Figure 13 shows the RAM and Flash memory organization. The transmit and receive RAM buffers share the same
address space and are both accessed using the RAMADDRH:RAMADDRL pointer. Each of the buffers has a
dedicated data register. The Flash memory has a separate address space and a dedicated address pointer and
data register. See “13. Flash Memory” on page 73 for detailed information on how to read and write to Flash.
7.1. Random Access to RAM Transmit and Receive Buffers
The most common and most efficient methods for accessing the transmit and receive buffers are the AutoWrite
and AutoRead interfaces. These interfaces allow entire packets to be written or read at a time. In very few cases,
the transmit and receive buffers may need to be accessed randomly. An example of this is a system in which a
specific byte in the packet is checked to determine whether to read the packet or discard it. The following
procedure can be used to read or write data to either RAM buffer:
Transmit Buffer (2K)
0x0000 – 0x07FF
Step 1: Write the address of the target byte to RAMADDRH:RAMADDRL.
Step 2: Transmit Buffer:
Read or write 8-bit data to RAMTXDATA to read or write from the target byte in the transmit buffer.
Receive Buffer:
Read or write 8-bit data to RAMRXDATA to read or write from the target byte in the receive buffer.
Note: Reads and writes of the RAM buffers using the random access method are independent of the
AutoRead and AutoWrite interfaces. Each of the interfaces has a dedicated set of address and data
registers. See “11.2. Transmitting a Packet” on page 48 and “12.2. Reading a Packet Using the
Autoread Interface” on page 58 for additional information about the AutoRead and AutoWrite
interfaces.
Figure 13. RAM Buffers and Flash Memory Organization
RAMADDRH:RAMADDRL
Receive Buffer (4K)
0x0000 – 0x0FFF
Rev. 1.0
FLASHADDRH:FLASHADDRL
Flash Memory (8K)
0x0000 – 0x1FFF
CP2200/1
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