cp2200 Silicon Laboratories, cp2200 Datasheet - Page 85

• Manufacturer Part Number: cp2200
• Description: Single-chip Ethernet Controller
• Manufacturer: Silicon Laboratories

Note: This register does not require initialization and will be left at its reset value will be set to 1518 (0x05EE)
Bits 15–0:MAXF: Maximum Frame Length
Note: This register does not require initialization and will be left at its reset value by most systems.
Bits 15–14:Reserved. Read = 00b; Must write 00b.
Bits 13–8:CW: Collision Window
Bits 7–4: Reserved. Read = 0000b; Must write 0000b.
Bits 3–0: MAXR: Maximum Retransmit Attempts
Indirect Register 5. CWMAXR: Collision Window and Maximum Retransmit Register
Bit15
R/W
R/W
Bit7
Bit15
R/W
R/W
Bit7
Reserved
by most systems.
Specifies the maximum length of a receive frame. The default value is 0x600 (1536 octets). This
register should be programmed if a shorter maximum length restriction is desired. Examples of
shorter frame lengths are untagged (1518 octets) and tagged (1522 octets). If a proprietary header
is allowed, this field should be adjusted accordingly.
Sets the collision window in which collisions occur in a properly configured network.
The collision window is specified in the number of bytes from the start of transmission. The pream-
ble and frame delimiter are included in the byte count. Its default of 0x37 corresponds to the count
of frame bytes at the end of the window.
Sets the maximum number of retransmit attempts following a collision before aborting the packet
due to excessive collisions. IEEE 802.3 specifies a maximum value of 0x0F (15d).
Indirect Register 6. MAXLEN: Maximum Frame Length Register
Bit14
R/W
R/W
Bit6
Bit14
R/W
R/W
Bit6
Reserved
Bit13
R/W
R/W
Bit5
Bit13
R/W
R/W
Bit5
Bit12
R/W
R/W
Bit4
Bit12
R/W
R/W
Bit4
Bit11
R/W
R/W
Bit3
Bit11
R/W
R/W
Bit3
Rev. 1.0
CW
Bit10
R/W
R/W
Bit2
Bit10
R/W
R/W
Bit2
MAXR
R/W
R/W
Bit9
Bit1
R/W
R/W
Bit9
Bit1
R/W
R/W
Bit8
Bit0
R/W
R/W
Bit8
Bit0
CP2200/1
Default Value
MACADDR:
Default Value
MACADDR:
0x0600
0x370F
0x05
0x04
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