cp2200 Silicon Laboratories, cp2200 Datasheet - Page 40
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cp2200
Manufacturer Part Number
cp2200
Description
Single-chip Ethernet Controller
Manufacturer
Silicon Laboratories
Datasheet
1.CP2200.pdf
(108 pages)
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CP2200/1
9.5. Software Reset
The software reset provides the host CPU the ability to reset the CP2200/1 through the parallel host interface.
Writing a ‘1’ to RESET (SWRST.2) will force the device to enter the reset state with the exception that the external
oscillator will not be stopped. As soon as the device enters the reset state, it will immediately exit the reset state
and start device calibration; the Oscillator Initialization Complete interrupt is not be generated. After Self
Initialization is complete, the device is fully functional.
Note: The software reset is enabled after every reset; however, it may be de-selected as a reset source (see the register
40
Bits 7–3: UNUSED. Read = 00000b, Write = don’t care.
Bit 2:
Bits 1–0: UNUSED. Read = 00b, Write = don’t care.
R\W
Bit7
description for RSTEN on page 42).
—
RESET: Software Reset Initiate
Writing a ‘1’ to this bit will generate a software reset.
R\W
Bit6
—
Register 12. SWRST: Software Reset Register
R/W
Bit5
—
R/W
Bit4
—
R/W
Bit3
—
Rev. 1.0
RESET
Bit2
W
R/W
Bit1
—
R/W
Bit0
—
00000000
Reset Value
Address:
0x75