cp2200 Silicon Laboratories, cp2200 Datasheet - Page 72

• Manufacturer Part Number: cp2200
• Description: Single-chip Ethernet Controller
• Manufacturer: Silicon Laboratories

CP2200/1
72
This register is set by hardware and is valid after an RX FIFO Full Interrupt is generated or
Bits 7–2: UNUSED. Read = 000000b, Write = don’t care.
Bits 1–0: FIFOSTA[1:0]: Receive FIFO Status
R/W
Bit7
—
if TLBVALID equals 0xFF.
00: Initial Value—No information.
01: The last packet successfully received used all available free space in the buffer.
10: The last packet successfully received was the 8th packet in the receive buffer. There is free
space remaining in the receive buffer; however, the maximum number of packets in the buffer has
been reached. Any future packets received will cause overflow.
Note: Receiving an unsuccessful 9th packet will cause overflow.
11: The last packet successfully received was the eighth packet in the receive buffer and used all
available free space in the buffer.
R/W
Bit6
—
Register 58. RXFIFOSTA: Receive FIFO Status Register
R/W
Bit5
—
R/W
Bit4
—
R/W
Bit3
—
Rev. 1.0
R/W
Bit2
—
FIFOSTA1 FIFOSTA0 00000000
R/W
Bit1
R/W
Bit0
Reset Value
Address:
0x5B