lan8187 Standard Microsystems Corp., lan8187 Datasheet - Page 32

• Manufacturer Part Number: lan8187
• Description: Lan8187/lan8187i ?15kv Esd Protected Mii/rmii 10/100 Ethernet Transceiver With Hp Auto-mdix & Flexpwr Technology
• Manufacturer: Standard Microsystems Corp.

Revision 1.5 (01-10-08)
4.10
4.11
4.12
4.12.1
The TX_ER, TXD4 and nINT functions share a common pin. There are two functional modes for this
pin, the TX_ER/TXD4 mode and nINT (interrupt) mode. The RXD3 pin is used to select one of these
two functional modes.
The RXD3 pin is latched on the rising edge of the internal reset (nreset) to select the mode. The
system designer must float the RXD3 pin for nINT mode or pull-low with an external resistor (see
Table 4.4, “Boot Strapping Configuration Resistors,” on page
TX_ER/TXD4 mode. The default setting is high (nINT mode).
The PHY ADDRESS bits are latched on the rising edge of the internal reset (nreset). The 5-bit address
word[0:4] is input on the LED1, LED2, LED3, LED4, GPO1 output pins. The default setting is all high
5'b1_1111.
The address lines are strapped as defined in the diagram below. The LED outputs will automatically
change polarity based on the presence of an external pull-down resistor. If the LED pin is pulled high
(by an internal 100K pull-up resistor) to select a logical high PHY address, then the LED output will
be active low. If the LED pin is pulled low (by an external pull-down resistor (see
Strapping Configuration Resistors,” on page
will then be an active high output.
To set the PHY address on the LED pins without LEDs or on the GPO1 or CRS pin, float the pin to
set the address high or pull-down the pin with an external resistor (see
Configuration Resistors,” on page
The Digital I/O pins on the LAN8187/LAN8187i are variable voltage to take advantage of low power
savings from shrinking technologies. These pins can operate from a low I/O voltage of +1.6V up to
+3.6V. Due to this low voltage feature addition, the system designer needs to take consideration as
for two aspects of their design. Boot strapping configuration and I/O voltage stability.
Boot Strapping Configuration.
Due to a lower I/O voltage, a lower strapping resistor needs to be used to ensure the strapped
configuration is latched into the PHY device at power-on reset.
(TX_ER/TXD4)/nINT Strapping
PHY Address Strapping and LED Output Polarity Selection
Variable Voltage I/O
LED output = active low
Phy Address = 1
Figure 4.5 PHY Address Strapping on LED’s
VDD
~270 ohms
±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR
33) to GND to set the address low. See the figure below:
DATASHEET
LED1-LED4
32
33) to select a logical low PHY address, the LED output
~10K ohms
LED output = active high
Phy Address = 0
33) to VSS to set the device in
Table 4.4, “Boot Strapping
~270 ohms
SMSC LAN8187/LAN8187i
LED1-LED4
Table 4.4, “Boot
TM
Datasheet
Technology