lan8187 Standard Microsystems Corp., lan8187 Datasheet - Page 52

• Manufacturer Part Number: lan8187
• Description: Lan8187/lan8187i ?15kv Esd Protected Mii/rmii 10/100 Ethernet Transceiver With Hp Auto-mdix & Flexpwr Technology
• Manufacturer: Standard Microsystems Corp.

Revision 1.5 (01-10-08)
5.4.5
5.4.5.1
5.4.5.2
5.4.6
Power-Down modes
There are 2 power-down modes for the Phy:
General Power-Down
This power-down is controlled by register 0, bit 11. In this mode the entire PHY, except the
management interface, is powered-down and stays in that condition as long as bit 0.11 is HIGH. When
bit 0.11 is cleared, the PHY powers up and is automatically reset.
Energy Detect Power-Down
This power-down mode is activated by setting bit 17.13 to 1. In this mode when no energy is present
on the line the PHY is powered down, except for the management interface, the SQUELCH circuit and
the ENERGYON logic. The ENERGYON logic is used to detect the presence of valid energy from
100Base-TX, 10Base-T, or Auto-negotiation signals
In this mode, when the ENERGYON signal is low, the PHY is powered-down, and nothing is
transmitted. When energy is received - link pulses or packets - the ENERGYON signal goes high, and
the PHY powers-up. It automatically resets itself into the state it had prior to power-down, and asserts
the nINT interrupt if the ENERGYON interrupt is enabled.
to activate ENERGYON may be lost.
When 17.13 is low, energy detect power-down is disabled.
Reset
The PHY has 3 reset sources:
Hardware reset (HWRST): connected to the nRST input, and to the internal POR signal.
If the nRST input is driven by an external source, it should be held LOW for at least 100 us to ensure
that the Phy is properly reset.
The Phy has an internal Power-On-Reset (POR) signal which is asserted for 21ms following a VDD33
(+3.3V) and VDDCORE (+1.8V) power-up. This internal POR is internally “OR”-ed with the nRST input.
During a Hardware reset, either external or POR, an external clock must be supplied to the CLKIN
signal.
Software (SW) reset: Activated by writing register 0, bit 15 high. This signal is self- clearing. After the
register-write, internal logic extends the reset by 256µs to allow PLL-stabilization before releasing the
logic from reset.
The IEEE 802.3u standard, clause 22 (22.2.4.1.1) states that the reset process should be completed
within 0.5s from the setting of this bit.
Power-Down reset: Automatically activated when the PHY comes out of power-down mode. The
internal power-down reset is extended by 256µs after exiting the power-down mode to allow the PLLs
to stabilize before the logic is released from reset.
These 3 reset sources are combined together in the digital block to create the internal “general reset”,
SYSRST, which is an asynchronous reset and is active HIGH. This SYSRST directly drives the PCS,
DSP and MII blocks. It is also input to the Central Bias block in order to generate a short reset for the
PLLs.
The SMI mechanism and registers are reset only by the Hardware and Software resets. During Power-
Down, the SMI registers are not reset. Note that some SMI register bits are not cleared by Software
reset – these are marked “NASR” in the register tables.
For the first 16us after coming out of reset, the MII will run at 2.5 MHz. After that it will switch to 25
MHz if auto-negotiation is enabled.
±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR
DATASHEET
52
The first and possibly the second packet
SMSC LAN8187/LAN8187i
TM
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